Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41818 )
Change subject: configs,mem-ruby: CHI-based Ruby protocol
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configs,mem-ruby: CHI-based Ruby protocol
This patch add a new Ruby cache coherence protocol based on Arm' AMBA5
CHI specification. The CHI protocol defines and implements two state
machine types:
- Cache_Controller: generic cache controller that can be configured as:
- Top-level L1 I/D cache
- A intermediate level (L2, L3, ...) private or shared cache
- A CHI home node (i.e. the point of coherence of the system and
has the global directory)
- A DMA requester
- Memory_Controller: implements a CHI slave node and interfaces with
gem5 memory controller. This controller has the functionality of a
Directory_Controller on the other Ruby protocols, except it doesn't
have a directory.
The Cache_Controller has multiple cache allocation/deallocation
parameters to control the clusivity with respect to upstream caches.
Allocation can be completely disabled to use Cache_Controller as a
DMA requester or as a home node without a shared LLC.
The standard configuration file configs/ruby/CHI.py provides a
'create_system' compatible with configs/example/fs.py and
configs/example/se.py and creates a system with private L1/L2 caches
per core and a shared LLC at the home nodes. Different cache topologies
can be defined by modifying 'create_system' or by creating custom
scripts using the structures defined in configs/ruby/CHI.py.
This patch also includes the 'CustomMesh' topology script to be used
with CHI. CustomMesh generates a 2D mesh topology with the placement
of components manually defined in a separate configuration file using
the --noc-config parameter.
The example in configs/example/noc_config/2x4.yaml creates a simple 2x4
mesh. For example, to run a SE mode simulation, with 4 cores,
4 mem ctnrls, and 4 home nodes (L3 caches):
build/ARM/gem5.opt configs/example/se.py \
--cmd 'tests/test-progs/hello/bin/arm/linux/hello' \
--ruby --num-cpus=4 --num-dirs=4 --num-l3caches=4 \
--topology=CustomMesh --noc-config=configs/example/noc_config/2x4.yaml
If one doesn't care about the component placement on the interconnect,
the 'Crossbar' and 'Pt2Pt' may be used and they do not require the
--noc-config option.
Additional authors:
Joshua Randall <joshua.rand...@arm.com>
Pedro Benedicte <pedro.benedicteilles...@arm.com>
Tuan Ta <tuan....@arm.com>
JIRA: https://gem5.atlassian.net/browse/GEM5-908
Change-Id: I856524b0afd30842194190f5bd69e7e6ded906b0
Signed-off-by: Tiago Mück <tiago.m...@arm.com>
---
A configs/example/noc_config/2x4.yaml
A configs/ruby/CHI.py
A configs/topologies/CustomMesh.py
M src/mem/ruby/SConscript
A src/mem/ruby/common/ExpectedMap.hh
A src/mem/ruby/common/TriggerQueue.hh
A src/mem/ruby/protocol/CHI-cache-actions.sm
A src/mem/ruby/protocol/CHI-cache-funcs.sm
A src/mem/ruby/protocol/CHI-cache-transitions.sm
A src/mem/ruby/protocol/CHI-cache.sm
A src/mem/ruby/protocol/CHI-mem.sm
A src/mem/ruby/protocol/CHI-msg.sm
A src/mem/ruby/protocol/CHI.slicc
M src/mem/ruby/protocol/RubySlicc_Exports.sm
M src/mem/ruby/protocol/SConsopts
M src/mem/ruby/system/SConscript
16 files changed, 9,358 insertions(+), 2 deletions(-)
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I856524b0afd30842194190f5bd69e7e6ded906b0
Gerrit-Change-Number: 41818
Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück <tiago.m...@arm.com>
Gerrit-MessageType: newchange
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