Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41996 )
Change subject: arch,sim: Get rid of unused "Packed" vector predicate
registers.
......................................................................
arch,sim: Get rid of unused "Packed" vector predicate registers.
Change-Id: Iecff7476bbd775e113788ced469fe85a467feede
---
M src/arch/arm/isa/insts/sve.isa
M src/arch/arm/registers.hh
M src/arch/arm/types.hh
M src/arch/generic/vec_pred_reg.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/registers.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/registers.hh
M src/arch/x86/registers.hh
M src/sim/insttracer.hh
11 files changed, 50 insertions(+), 78 deletions(-)
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index 03775ca..354fe65 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -2396,8 +2396,8 @@
extraPrologCode = ''
if isFlagSetting:
code += '''
- VecPredRegT<uint8_t, MaxSveVecLenInBytes, false, false>::Container
c;
- VecPredRegT<uint8_t, MaxSveVecLenInBytes, false, false>
predOnes(c);
+ VecPredRegT<uint8_t, MaxSveVecLenInBytes, false>::Container c;
+ VecPredRegT<uint8_t, MaxSveVecLenInBytes, false> predOnes(c);
for (unsigned i = 0; i < eCount; i++) {
predOnes[i] = 1;
}
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 62fb0d3..663b83a 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -61,10 +61,8 @@
using VecRegContainer =
::VecRegContainer<NumVecElemPerVecReg * sizeof(VecElem)>;
-using VecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg,
- VecPredRegHasPackedRepr, false>;
-using ConstVecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg,
- VecPredRegHasPackedRepr, true>;
+using VecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg, false>;
+using ConstVecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg, true>;
using VecPredRegContainer = VecPredReg::Container;
// Constants Related to the number of registers
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index fa877be..f2c997f 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -817,7 +817,6 @@
constexpr unsigned VecRegSizeBytes = MaxSveVecLenInBytes;
constexpr unsigned VecPredRegSizeBits = MaxSveVecLenInBytes;
- constexpr unsigned VecPredRegHasPackedRepr = false;
} // namespace ArmISA
#endif
diff --git a/src/arch/generic/vec_pred_reg.hh
b/src/arch/generic/vec_pred_reg.hh
index 84047f6..67ee9e5 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -43,7 +43,7 @@
#include "arch/generic/vec_reg.hh"
#include "base/cprintf.hh"
-template <size_t NumBits, bool Packed>
+template <size_t NumBits>
class VecPredRegContainer;
/// Predicate register view.
@@ -54,32 +54,25 @@
/// templated on the vector element type to simplify ISA definitions.
/// @tparam VecElem Type of the vector elements.
/// @tparam NumElems Number of vector elements making up the view.
-/// @tparam Packed True if the predicate register relies on a packed
-/// representation, i.e. adjacent bits refer to different vector elements
-/// irrespective of the vector element size (e.g. this is the case for
-/// AVX-512). If false, the predicate register relies on an unpacked
-/// representation, where each bit refers to the corresponding byte in a
vector
-/// register (e.g. this is the case for ARM SVE).
/// @tparam Const True if the underlying container can be modified through
/// the view.
-template <typename VecElem, size_t NumElems, bool Packed, bool Const>
+template <typename VecElem, size_t NumElems, bool Const>
class VecPredRegT
{
protected:
/// Size of the register in bits.
- static constexpr size_t NUM_BITS = Packed ? NumElems :
- sizeof(VecElem) * NumElems;
+ static constexpr size_t NUM_BITS = sizeof(VecElem) * NumElems;
public:
/// Container type alias.
using Container = typename std::conditional<
Const,
- const VecPredRegContainer<NUM_BITS, Packed>,
- VecPredRegContainer<NUM_BITS, Packed>>::type;
+ const VecPredRegContainer<NUM_BITS>,
+ VecPredRegContainer<NUM_BITS>>::type;
protected:
// Alias for this type
- using MyClass = VecPredRegT<VecElem, NumElems, Packed, Const>;
+ using MyClass = VecPredRegT<VecElem, NumElems, Const>;
/// Container corresponding to this view.
Container& container;
@@ -88,13 +81,11 @@
/// Reset the register to an all-false value.
template<bool Condition = !Const>
- typename std::enable_if_t<Condition, void>
- reset() { container.reset(); }
+ typename std::enable_if_t<Condition, void> reset() {
container.reset(); }
/// Reset the register to an all-true value.
template<bool Condition = !Const>
- typename std::enable_if_t<Condition, void>
- set() { container.set(); }
+ typename std::enable_if_t<Condition, void> set() { container.set(); }
template<bool Condition = !Const>
typename std::enable_if_t<Condition, MyClass&>
@@ -107,14 +98,14 @@
const bool&
operator[](size_t idx) const
{
- return container[idx * (Packed ? 1 : sizeof(VecElem))];
+ return container[idx * sizeof(VecElem)];
}
template<bool Condition = !Const>
typename std::enable_if_t<Condition, bool&>
operator[](size_t idx)
{
- return container[idx * (Packed ? 1 : sizeof(VecElem))];
+ return container[idx * sizeof(VecElem)];
}
/// Return an element of the predicate register as it appears
@@ -122,8 +113,7 @@
uint8_t
get_raw(size_t idx) const
{
- return container.get_bits(idx * (Packed ? 1 : sizeof(VecElem)),
- (Packed ? 1 : sizeof(VecElem)));
+ return container.get_bits(idx * sizeof(VecElem), sizeof(VecElem));
}
/// Write a raw value in an element of the predicate register
@@ -131,22 +121,21 @@
typename std::enable_if_t<Condition, void>
set_raw(size_t idx, uint8_t val)
{
- container.set_bits(idx * (Packed ? 1 : sizeof(VecElem)),
- (Packed ? 1 : sizeof(VecElem)), val);
+ container.set_bits(idx * sizeof(VecElem), sizeof(VecElem), val);
}
/// Equality operator, required to compare thread contexts.
- template<typename VE2, size_t NE2, bool P2, bool C2>
+ template<typename VE2, size_t NE2, bool C2>
bool
- operator==(const VecPredRegT<VE2, NE2, P2, C2>& that) const
+ operator==(const VecPredRegT<VE2, NE2, C2>& that) const
{
return container == that.container;
}
/// Inequality operator, required to compare thread contexts.
- template<typename VE2, size_t NE2, bool P2, bool C2>
+ template<typename VE2, size_t NE2, bool C2>
bool
- operator!=(const VecPredRegT<VE2, NE2, P2, C2>& that) const
+ operator!=(const VecPredRegT<VE2, NE2, C2>& that) const
{
return !operator==(that);
}
@@ -172,7 +161,7 @@
/// the test (corresponding to the current vector length).
template <bool MC>
bool
- firstActive(const VecPredRegT<VecElem, NumElems, Packed, MC>& mask,
+ firstActive(const VecPredRegT<VecElem, NumElems, MC>& mask,
size_t actual_num_elems) const
{
assert(actual_num_elems <= NumElems);
@@ -190,7 +179,7 @@
/// the test (corresponding to the current vector length).
template <bool MC>
bool
- noneActive(const VecPredRegT<VecElem, NumElems, Packed, MC>& mask,
+ noneActive(const VecPredRegT<VecElem, NumElems, MC>& mask,
size_t actual_num_elems) const
{
assert(actual_num_elems <= NumElems);
@@ -208,7 +197,7 @@
/// the test (corresponding to the current vector length).
template <bool MC>
bool
- lastActive(const VecPredRegT<VecElem, NumElems, Packed, MC>& mask,
+ lastActive(const VecPredRegT<VecElem, NumElems, MC>& mask,
size_t actual_num_elems) const
{
assert(actual_num_elems <= NumElems);
@@ -226,8 +215,7 @@
/// This generic class implements the Model in an MVC pattern, similarly to
/// @see VecRegContainer.
/// @tparam NumBits Size of the container in bits.
-/// @tparam Packed See @VecRegT.
-template <size_t NumBits, bool Packed>
+template <size_t NumBits>
class VecPredRegContainer
{
static_assert(NumBits > 0,
@@ -240,7 +228,7 @@
private:
Container container;
// Alias for this type
- using MyClass = VecPredRegContainer<NumBits, Packed>;
+ using MyClass = VecPredRegContainer<NumBits>;
public:
VecPredRegContainer() {}
@@ -279,17 +267,17 @@
}
/// Equality operator, required to compare thread contexts.
- template<size_t N2, bool P2>
+ template<size_t N2>
inline bool
- operator==(const VecPredRegContainer<N2, P2>& that) const
+ operator==(const VecPredRegContainer<N2>& that) const
{
- return NumBits == N2 && Packed == P2 && container ==
that.container;
+ return NumBits == N2 && container == that.container;
}
/// Inequality operator, required to compare thread contexts.
- template<size_t N2, bool P2>
+ template<size_t N2>
bool
- operator!=(const VecPredRegContainer<N2, P2>& that) const
+ operator!=(const VecPredRegContainer<N2>& that) const
{
return !operator==(that);
}
@@ -347,36 +335,32 @@
/// @tparam VecElem Type of the vector elements.
/// @tparam NumElems Number of vector elements making up the view.
/// @{
- template <typename VecElem,
- size_t NumElems = (Packed ? NumBits : NumBits /
sizeof(VecElem))>
- VecPredRegT<VecElem, NumElems, Packed, true> as() const
+ template <typename VecElem, size_t NumElems = NumBits /
sizeof(VecElem)>
+ VecPredRegT<VecElem, NumElems, true>
+ as() const
{
- static_assert((Packed && NumElems <= NumBits) ||
- (!Packed &&
- NumBits % sizeof(VecElem) == 0 &&
- sizeof(VecElem) * NumElems <= NumBits),
+ static_assert(NumBits % sizeof(VecElem) == 0 &&
+ sizeof(VecElem) * NumElems <= NumBits,
"Container size incompatible with view size");
- return VecPredRegT<VecElem, NumElems, Packed, true>(*this);
+ return VecPredRegT<VecElem, NumElems, true>(*this);
}
- template <typename VecElem,
- size_t NumElems = (Packed ? NumBits : NumBits /
sizeof(VecElem))>
- VecPredRegT<VecElem, NumElems, Packed, false> as()
+ template <typename VecElem, size_t NumElems = NumBits /
sizeof(VecElem)>
+ VecPredRegT<VecElem, NumElems, false>
+ as()
{
- static_assert((Packed && NumElems <= NumBits) ||
- (!Packed &&
- NumBits % sizeof(VecElem) == 0 &&
- sizeof(VecElem) * NumElems <= NumBits),
+ static_assert(NumBits % sizeof(VecElem) == 0 &&
+ sizeof(VecElem) * NumElems <= NumBits,
"Container size incompatible with view size");
- return VecPredRegT<VecElem, NumElems, Packed, false>(*this);
+ return VecPredRegT<VecElem, NumElems, false>(*this);
}
/// @}
};
/// Helper functions used for serialization/de-serialization
-template <size_t NumBits, bool Packed>
+template <size_t NumBits>
inline bool
-to_number(const std::string& value, VecPredRegContainer<NumBits, Packed>&
p)
+to_number(const std::string& value, VecPredRegContainer<NumBits>& p)
{
int i = 0;
for (const auto& c: value) {
@@ -388,12 +372,11 @@
/// Dummy type aliases and constants for architectures that do not
implement
/// vector predicate registers.
/// @{
-constexpr bool DummyVecPredRegHasPackedRepr = false;
using DummyVecPredReg = VecPredRegT<DummyVecElem, DummyNumVecElemPerVecReg,
- DummyVecPredRegHasPackedRepr, false>;
+ false>;
using DummyConstVecPredReg = VecPredRegT<DummyVecElem,
DummyNumVecElemPerVecReg,
- DummyVecPredRegHasPackedRepr,
true>;
+ true>;
using DummyVecPredRegContainer = DummyVecPredReg::Container;
constexpr size_t DummyVecPredRegSizeBits = 8;
/// @}
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 18c0d58..4ca73d8 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -279,7 +279,6 @@
using ConstVecPredReg = ::DummyConstVecPredReg;
using VecPredRegContainer = ::DummyVecPredRegContainer;
constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
-constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
} // namespace MipsISA
diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index d56a6a7..aa01945 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -58,7 +58,6 @@
using ConstVecPredReg = ::DummyConstVecPredReg;
using VecPredRegContainer = ::DummyVecPredRegContainer;
constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
-constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
}
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 5fc2200..5f5f67b 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -48,7 +48,6 @@
using ConstVecPredReg = ::DummyConstVecPredReg;
using VecPredRegContainer = ::DummyVecPredRegContainer;
constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
-constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
// Constants Related to the number of registers
const int NumIntArchRegs = 32;
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index e7f3e11..126132f 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -102,7 +102,6 @@
using ConstVecPredReg = ::DummyConstVecPredReg;
using VecPredRegContainer = ::DummyVecPredRegContainer;
constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
-constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
const int NumIntArchRegs = 32;
const int NumMicroIntRegs = 1;
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index aa263a9..bf92f02 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -49,7 +49,6 @@
using ConstVecPredReg = ::DummyConstVecPredReg;
using VecPredRegContainer = ::DummyVecPredRegContainer;
constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
-constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
// semantically meaningful register indices
enum {
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 769f6da..867ad9a 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -92,7 +92,6 @@
using ConstVecPredReg = ::DummyConstVecPredReg;
using VecPredRegContainer = ::DummyVecPredRegContainer;
constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
-constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
} // namespace X86ISA
diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index 22e2489..636bf76 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -95,8 +95,7 @@
uint64_t as_int;
double as_double;
::VecRegContainer<TheISA::VecRegSizeBytes>* as_vec;
- ::VecPredRegContainer<TheISA::VecPredRegSizeBits,
- TheISA::VecPredRegHasPackedRepr>* as_pred;
+ ::VecPredRegContainer<TheISA::VecPredRegSizeBits>* as_pred;
} data;
/** @defgroup fetch_seq
@@ -209,11 +208,10 @@
}
void
- setData(::VecPredRegContainer<TheISA::VecPredRegSizeBits,
- TheISA::VecPredRegHasPackedRepr>& d)
+ setData(::VecPredRegContainer<TheISA::VecPredRegSizeBits>& d)
{
- data.as_pred = new ::VecPredRegContainer<
- TheISA::VecPredRegSizeBits,
TheISA::VecPredRegHasPackedRepr>(d);
+ data.as_pred =
+ new ::VecPredRegContainer<TheISA::VecPredRegSizeBits>(d);
data_status = DataVecPred;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iecff7476bbd775e113788ced469fe85a467feede
Gerrit-Change-Number: 41996
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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