Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/42001 )
Change subject: cpu: Use the built in << for VecReg and VecPredReg in
ExeTrace.
......................................................................
cpu: Use the built in << for VecReg and VecPredReg in ExeTrace.
There's no reason to reimplement printing code when VecReg and
VecPredReg types already know how to print themselves.
Change-Id: I092c28143de286d765312122b81ce865a5184091
---
M src/cpu/exetrace.cc
1 file changed, 2 insertions(+), 23 deletions(-)
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 76db4d7..cf4a734 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -116,31 +116,10 @@
if (Debug::ExecResult && data_status != DataInvalid) {
switch (data_status) {
case DataVec:
- {
- ccprintf(outs, " D=0x[");
- auto dv = data.as_vec->as<uint32_t>();
- for (int i = TheISA::VecRegSizeBytes / 4 - 1; i >= 0;
- i--) {
- ccprintf(outs, "%08x", dv[i]);
- if (i != 0) {
- ccprintf(outs, "_");
- }
- }
- ccprintf(outs, "]");
- }
+ ccprintf(outs, " D=%s", *data.as_vec);
break;
case DataVecPred:
- {
- ccprintf(outs, " D=0b[");
- auto pv = data.as_pred->as<uint8_t>();
- for (int i = TheISA::VecPredRegSizeBits - 1; i >= 0;
i--) {
- ccprintf(outs, pv[i] ? "1" : "0");
- if (i != 0 && i % 4 == 0) {
- ccprintf(outs, "_");
- }
- }
- ccprintf(outs, "]");
- }
+ ccprintf(outs, " D=%s", *data.as_pred);
break;
default:
ccprintf(outs, " D=%#018x", data.as_int);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I092c28143de286d765312122b81ce865a5184091
Gerrit-Change-Number: 42001
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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