Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41815 )
Change subject: mem-ruby: notify controller on coalescing
......................................................................
mem-ruby: notify controller on coalescing
Sequencer notifies controllers when coalescing requests.
notifyCoalesced can be overridden by protocols to, for instance,
account for coalesced requests in hit/miss stats and/or prefetcher
training.
Change-Id: Ia9c8d64cac2cd3ce859a76a1dc1324e3fc6a7b90
Signed-off-by: Tiago Mück <tiago.m...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41815
Maintainer: Jason Lowe-Power <power...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
---
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
3 files changed, 27 insertions(+), 9 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 079bdd3..4b632db 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -137,6 +137,15 @@
virtual void enqueuePrefetch(const Addr &, const RubyRequestType&)
{ fatal("Prefetches not implemented!");}
+ //! Notifies controller of a request coalesced at the sequencer.
+ //! By default, it does nothing. Behavior is protocol-specific
+ virtual void notifyCoalesced(const Addr& addr,
+ const RubyRequestType& type,
+ const RequestPtr& req,
+ const DataBlock& data_blk,
+ const bool& was_miss)
+ { }
+
//! Function for collating statistics from all the controllers of this
//! particular type. This function should only be called from the
//! version 0 of this controller type.
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index 0a80905..58cace6 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -473,19 +473,18 @@
aliased_stores++;
}
markRemoved();
- ruby_request = false;
hitCallback(&seq_req, data, success, mach, externalHit,
initialRequestTime, forwardRequestTime,
- firstResponseTime);
+ firstResponseTime, !ruby_request);
+ ruby_request = false;
} else {
// handle read request
assert(!ruby_request);
markRemoved();
- ruby_request = false;
aliased_loads++;
hitCallback(&seq_req, data, true, mach, externalHit,
initialRequestTime, forwardRequestTime,
- firstResponseTime);
+ firstResponseTime, !ruby_request);
}
seq_req_list.pop_front();
}
@@ -538,10 +537,10 @@
firstResponseTime);
}
markRemoved();
- ruby_request = false;
hitCallback(&seq_req, data, true, mach, externalHit,
initialRequestTime, forwardRequestTime,
- firstResponseTime);
+ firstResponseTime, !ruby_request);
+ ruby_request = false;
seq_req_list.pop_front();
}
@@ -557,7 +556,8 @@
const MachineType mach, const bool externalHit,
const Cycles initialRequestTime,
const Cycles forwardRequestTime,
- const Cycles firstResponseTime)
+ const Cycles firstResponseTime,
+ const bool was_coalesced)
{
warn_once("Replacement policy updates recently became the
responsibility "
"of SLICC state machines. Make sure to setMRU() near
callbacks "
@@ -567,6 +567,14 @@
Addr request_address(pkt->getAddr());
RubyRequestType type = srequest->m_type;
+ if (was_coalesced) {
+ // Notify the controller about a coalesced request so it can
properly
+ // account for it in its hit/miss stats and/or train prefetchers
+ // (this is protocol-dependent)
+ m_controller->notifyCoalesced(request_address, type, pkt->req,
+ data, externalHit);
+ }
+
// Load-linked handling
if (type == RubyRequestType_Load_Linked) {
Addr line_addr = makeLineAddress(request_address);
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index 904d764..d8ffb86 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 ARM Limited
+ * Copyright (c) 2019-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -193,7 +193,8 @@
const MachineType mach, const bool externalHit,
const Cycles initialRequestTime,
const Cycles forwardRequestTime,
- const Cycles firstResponseTime);
+ const Cycles firstResponseTime,
+ const bool was_coalesced);
void recordMissLatency(SequencerRequest* srequest, bool llscSuccess,
const MachineType respondingMach,
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia9c8d64cac2cd3ce859a76a1dc1324e3fc6a7b90
Gerrit-Change-Number: 41815
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück <tiago.m...@arm.com>
Gerrit-Reviewer: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-Reviewer: Tiago Mück <tiago.m...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: merged
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