Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/42099 )
Change subject: cpu: Pull all remaining non-comm types out of
SimpleCPUPolicy.
......................................................................
cpu: Pull all remaining non-comm types out of SimpleCPUPolicy.
Change-Id: I79c56533cf6a9d1c982cea3ca9bedc83e6afda49
---
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/cpu_policy.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/iew.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
13 files changed, 59 insertions(+), 85 deletions(-)
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index f4c1305..ce5c889 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -48,6 +48,8 @@
#include "cpu/inst_seq.hh"
#include "cpu/o3/iew.hh"
#include "cpu/o3/limits.hh"
+#include "cpu/o3/rename_map.hh"
+#include "cpu/o3/rob.hh"
#include "cpu/timebuf.hh"
#include "enums/CommitPolicy.hh"
#include "sim/probe/probe.hh"
@@ -88,9 +90,6 @@
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::CPUPol CPUPol;
- typedef typename CPUPol::RenameMap RenameMap;
- typedef typename CPUPol::ROB ROB;
-
typedef typename CPUPol::TimeStruct TimeStruct;
typedef typename CPUPol::FetchStruct FetchStruct;
typedef typename CPUPol::IEWStruct IEWStruct;
@@ -172,10 +171,10 @@
void setActiveThreads(std::list<ThreadID> *at_ptr);
/** Sets pointer to the commited state rename map. */
- void setRenameMap(RenameMap rm_ptr[O3MaxThreads]);
+ void setRenameMap(UnifiedRenameMap rm_ptr[O3MaxThreads]);
/** Sets pointer to the ROB. */
- void setROB(ROB *rob_ptr);
+ void setROB(ROB<Impl> *rob_ptr);
/** Initializes stage by sending back the number of free entries. */
void startupStage();
@@ -354,7 +353,7 @@
public:
/** ROB interface. */
- ROB *rob;
+ ROB<Impl> *rob;
private:
/** Pointer to O3CPU. */
@@ -461,7 +460,7 @@
std::list<ThreadID> *activeThreads;
/** Rename map interface. */
- RenameMap *renameMap[O3MaxThreads];
+ UnifiedRenameMap *renameMap[O3MaxThreads];
/** True if last committed microop can be followed by an interrupt */
bool canHandleInterrupts;
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index c72c83c..4e5d05e 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -305,7 +305,7 @@
template <class Impl>
void
-DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
+DefaultCommit<Impl>::setRenameMap(UnifiedRenameMap rm_ptr[])
{
for (ThreadID tid = 0; tid < numThreads; tid++)
renameMap[tid] = &rm_ptr[tid];
@@ -313,7 +313,7 @@
template <class Impl>
void
-DefaultCommit<Impl>::setROB(ROB *rob_ptr)
+DefaultCommit<Impl>::setROB(ROB<Impl> *rob_ptr)
{
rob = rob_ptr;
}
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 2bc1fd4..9f0d001 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -58,9 +58,11 @@
#include "cpu/o3/cpu_policy.hh"
#include "cpu/o3/decode.hh"
#include "cpu/o3/fetch.hh"
+#include "cpu/o3/free_list.hh"
#include "cpu/o3/iew.hh"
#include "cpu/o3/limits.hh"
#include "cpu/o3/rename.hh"
+#include "cpu/o3/rob.hh"
#include "cpu/o3/scoreboard.hh"
#include "cpu/o3/thread_state.hh"
#include "cpu/activity.hh"
@@ -564,16 +566,16 @@
PhysRegFile regFile;
/** The free list. */
- typename CPUPolicy::FreeList freeList;
+ UnifiedFreeList freeList;
/** The rename map. */
- typename CPUPolicy::RenameMap renameMap[O3MaxThreads];
+ UnifiedRenameMap renameMap[O3MaxThreads];
/** The commit rename map. */
- typename CPUPolicy::RenameMap commitRenameMap[O3MaxThreads];
+ UnifiedRenameMap commitRenameMap[O3MaxThreads];
/** The re-order buffer. */
- typename CPUPolicy::ROB rob;
+ ROB<Impl> rob;
/** Active Threads List */
std::list<ThreadID> activeThreads;
diff --git a/src/cpu/o3/cpu_policy.hh b/src/cpu/o3/cpu_policy.hh
index c5af880..e016548 100644
--- a/src/cpu/o3/cpu_policy.hh
+++ b/src/cpu/o3/cpu_policy.hh
@@ -31,15 +31,6 @@
#define __CPU_O3_CPU_POLICY_HH__
#include "cpu/o3/comm.hh"
-#include "cpu/o3/free_list.hh"
-#include "cpu/o3/inst_queue.hh"
-#include "cpu/o3/lsq.hh"
-#include "cpu/o3/lsq_unit.hh"
-#include "cpu/o3/mem_dep_unit.hh"
-#include "cpu/o3/regfile.hh"
-#include "cpu/o3/rename_map.hh"
-#include "cpu/o3/rob.hh"
-#include "cpu/o3/store_set.hh"
/**
* Struct that defines the key classes to be used by the CPU. All
@@ -53,21 +44,6 @@
template<class Impl>
struct SimpleCPUPolicy
{
- /** Typedef for the freelist of registers. */
- typedef UnifiedFreeList FreeList;
- /** Typedef for the rename map. */
- typedef UnifiedRenameMap RenameMap;
- /** Typedef for the ROB. */
- typedef ::ROB<Impl> ROB;
- /** Typedef for the instruction queue/scheduler. */
- typedef InstructionQueue<Impl> IQ;
- /** Typedef for the memory dependence unit. */
- typedef ::MemDepUnit<StoreSet, Impl> MemDepUnit;
- /** Typedef for the LSQ. */
- typedef ::LSQ<Impl> LSQ;
- /** Typedef for the thread-specific LSQ units. */
- typedef ::LSQUnit<Impl> LSQUnit;
-
/** The struct for communication between fetch and decode. */
typedef DefaultFetchDefaultDecode<Impl> FetchStruct;
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index bc4bd10..65fc680 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -58,6 +58,7 @@
#include "cpu/inst_seq.hh"
#include "cpu/o3/cpu.hh"
#include "cpu/o3/isa_specific.hh"
+#include "cpu/o3/lsq_unit.hh"
#include "cpu/op_class.hh"
#include "cpu/reg_class.hh"
#include "cpu/static_inst.hh"
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
index 3bfabdb..7a2a92a 100644
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -46,6 +46,7 @@
#include "base/statistics.hh"
#include "cpu/o3/comm.hh"
+#include "cpu/o3/inst_queue.hh"
#include "cpu/o3/limits.hh"
#include "cpu/o3/lsq.hh"
#include "cpu/o3/scoreboard.hh"
@@ -84,10 +85,6 @@
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::O3CPU O3CPU;
- typedef typename CPUPol::IQ IQ;
- typedef typename CPUPol::RenameMap RenameMap;
- typedef typename CPUPol::LSQ LSQ;
-
typedef typename CPUPol::TimeStruct TimeStruct;
typedef typename CPUPol::IEWStruct IEWStruct;
typedef typename CPUPol::RenameStruct RenameStruct;
@@ -362,10 +359,10 @@
public:
/** Instruction queue. */
- IQ instQueue;
+ InstructionQueue<Impl> instQueue;
/** Load / store queue. */
- LSQ ldstQueue;
+ LSQ<Impl> ldstQueue;
/** Pointer to the functional unit pool. */
FUPool *fuPool;
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index b750354..248b8a2 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -51,8 +51,9 @@
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/dep_graph.hh"
-#include "cpu/o3/iew.hh"
#include "cpu/o3/limits.hh"
+#include "cpu/o3/mem_dep_unit.hh"
+#include "cpu/o3/store_set.hh"
#include "cpu/op_class.hh"
#include "cpu/timebuf.hh"
#include "enums/SMTQueuePolicy.hh"
@@ -62,6 +63,9 @@
class FUPool;
class MemInterface;
+template <class Impl>
+class DefaultIEW;
+
/**
* A standard instruction queue class. It holds ready instructions, in
* order, in seperate priority queues to facilitate the scheduling of
@@ -87,7 +91,6 @@
typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr;
- typedef typename Impl::CPUPol::MemDepUnit MemDepUnit;
typedef typename Impl::CPUPol::IssueStruct IssueStruct;
typedef typename Impl::CPUPol::TimeStruct TimeStruct;
@@ -286,7 +289,7 @@
/** The memory dependence unit, which tracks/predicts memory
dependences
* between instructions.
*/
- MemDepUnit memDepUnit[O3MaxThreads];
+ MemDepUnit<StoreSet, Impl> memDepUnit[O3MaxThreads];
/** The queue to the execute stage. Issued instructions will be
written
* into it.
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 95bf258..e7e1f27 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -53,7 +53,6 @@
#include "base/flags.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
-#include "cpu/o3/lsq_unit.hh"
#include "cpu/utils.hh"
#include "enums/SMTQueuePolicy.hh"
#include "mem/port.hh"
@@ -68,13 +67,14 @@
class DefaultIEW;
template <class Impl>
-class LSQ
+class LSQUnit;
+template <class Impl>
+class LSQ
{
public:
typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr;
- typedef typename Impl::CPUPol::LSQUnit LSQUnit;
class LSQRequest;
/** Derived class to hold any sender state the LSQ needs. */
@@ -292,7 +292,7 @@
bool isDelayed() { return flags.isSet(Flag::Delayed); }
public:
- LSQUnit& _port;
+ LSQUnit<Impl>& _port;
const DynInstPtr _inst;
uint32_t _taskId;
PacketDataPtr _data;
@@ -307,8 +307,8 @@
uint32_t _numOutstandingPackets;
AtomicOpFunctorPtr _amo_op;
protected:
- LSQUnit* lsqUnit() { return &_port; }
- LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad) :
+ LSQUnit<Impl>* lsqUnit() { return &_port; }
+ LSQRequest(LSQUnit<Impl> *port, const DynInstPtr& inst, bool
isLoad) :
_state(State::NotIssued), _senderState(nullptr),
_port(*port), _inst(inst), _data(nullptr),
_res(nullptr), _addr(0), _size(0), _flags(0),
@@ -320,7 +320,7 @@
flags.set(Flag::IsAtomic, _inst->isAtomic());
install();
}
- LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad,
+ LSQRequest(LSQUnit<Impl>* port, const DynInstPtr& inst, bool
isLoad,
const Addr& addr, const uint32_t& size,
const Request::Flags& flags_,
PacketDataPtr data = nullptr, uint64_t* res = nullptr,
@@ -728,12 +728,10 @@
using LSQRequest::_numOutstandingPackets;
using LSQRequest::_amo_op;
public:
- SingleDataRequest(LSQUnit* port, const DynInstPtr& inst, bool
isLoad,
- const Addr& addr, const uint32_t& size,
- const Request::Flags& flags_,
- PacketDataPtr data = nullptr,
- uint64_t* res = nullptr,
- AtomicOpFunctorPtr amo_op = nullptr) :
+ SingleDataRequest(LSQUnit<Impl>* port, const DynInstPtr& inst,
+ bool isLoad, const Addr& addr, const uint32_t& size,
+ const Request::Flags& flags_, PacketDataPtr data=nullptr,
+ uint64_t* res=nullptr, AtomicOpFunctorPtr amo_op=nullptr) :
LSQRequest(port, inst, isLoad, addr, size, flags_, data, res,
std::move(amo_op)) {}
@@ -768,8 +766,8 @@
using LSQRequest::flags;
using LSQRequest::setState;
public:
- HtmCmdRequest(LSQUnit* port, const DynInstPtr& inst,
- const Request::Flags& flags_);
+ HtmCmdRequest(LSQUnit<Impl>* port, const DynInstPtr& inst,
+ const Request::Flags& flags_);
inline virtual ~HtmCmdRequest() {}
virtual void initiateTranslation();
virtual void finish(const Fault &fault, const RequestPtr &req,
@@ -815,11 +813,10 @@
PacketPtr _mainPacket;
public:
- SplitDataRequest(LSQUnit* port, const DynInstPtr& inst, bool
isLoad,
- const Addr& addr, const uint32_t& size,
- const Request::Flags & flags_,
- PacketDataPtr data = nullptr,
- uint64_t* res = nullptr) :
+ SplitDataRequest(LSQUnit<Impl>* port, const DynInstPtr& inst,
+ bool isLoad, const Addr& addr, const uint32_t& size,
+ const Request::Flags & flags_, PacketDataPtr data=nullptr,
+ uint64_t* res=nullptr) :
LSQRequest(port, inst, isLoad, addr, size, flags_, data, res,
nullptr),
numFragments(0),
@@ -1185,7 +1182,7 @@
DcachePort dcachePort;
/** The LSQ units for individual threads. */
- std::vector<LSQUnit> thread;
+ std::vector<LSQUnit<Impl>> thread;
/** Number of Threads. */
ThreadID numThreads;
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index acd4a69..cddb1d5 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -1224,7 +1224,7 @@
}
template<class Impl>
-LSQ<Impl>::HtmCmdRequest::HtmCmdRequest(LSQUnit* port,
+LSQ<Impl>::HtmCmdRequest::HtmCmdRequest(LSQUnit<Impl>* port,
const DynInstPtr& inst,
const Request::Flags& flags_) :
SingleDataRequest(port, inst, true, 0x0lu, 8, flags_,
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 1257448..28fb7be 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -53,6 +53,7 @@
#include "arch/locked_mem.hh"
#include "config/the_isa.hh"
#include "cpu/inst_seq.hh"
+#include "cpu/o3/lsq.hh"
#include "cpu/timebuf.hh"
#include "debug/HtmCpu.hh"
#include "debug/LSQUnit.hh"
@@ -85,11 +86,10 @@
typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr;
- typedef typename Impl::CPUPol::LSQ LSQ;
typedef typename Impl::CPUPol::IssueStruct IssueStruct;
- using LSQSenderState = typename LSQ::LSQSenderState;
- using LSQRequest = typename Impl::CPUPol::LSQ::LSQRequest;
+ using LSQSenderState = typename LSQ<Impl>::LSQSenderState;
+ using LSQRequest = typename LSQ<Impl>::LSQRequest;
private:
class LSQEntry
{
@@ -235,7 +235,7 @@
/** Initializes the LSQ unit with the specified number of entries. */
void init(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
- const DerivO3CPUParams ¶ms, LSQ *lsq_ptr, unsigned id);
+ const DerivO3CPUParams ¶ms, LSQ<Impl> *lsq_ptr, unsigned
id);
/** Returns the name of the LSQ unit. */
std::string name() const;
@@ -413,7 +413,7 @@
DefaultIEW<Impl> *iewStage;
/** Pointer to the LSQ. */
- LSQ *lsq;
+ LSQ<Impl> *lsq;
/** Pointer to the dcache port. Used only for sending. */
RequestPort *dcachePort;
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 71d02f1..525f19d 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -216,7 +216,7 @@
template<class Impl>
void
LSQUnit<Impl>::init(O3CPU *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
- const DerivO3CPUParams ¶ms, LSQ *lsq_ptr, unsigned id)
+ const DerivO3CPUParams ¶ms, LSQ<Impl> *lsq_ptr, unsigned id)
{
lsqID = id;
diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh
index f582789..17734ec 100644
--- a/src/cpu/o3/rename.hh
+++ b/src/cpu/o3/rename.hh
@@ -48,6 +48,7 @@
#include "base/statistics.hh"
#include "config/the_isa.hh"
#include "cpu/o3/commit.hh"
+#include "cpu/o3/free_list.hh"
#include "cpu/o3/iew.hh"
#include "cpu/o3/limits.hh"
#include "cpu/timebuf.hh"
@@ -80,8 +81,6 @@
typedef typename CPUPol::DecodeStruct DecodeStruct;
typedef typename CPUPol::RenameStruct RenameStruct;
typedef typename CPUPol::TimeStruct TimeStruct;
- typedef typename CPUPol::FreeList FreeList;
- typedef typename CPUPol::RenameMap RenameMap;
// A deque is used to queue the instructions. Barrier insts must
// be added to the front of the queue, which is the only reason for
@@ -171,10 +170,10 @@
void setActiveThreads(std::list<ThreadID> *at_ptr);
/** Sets pointer to rename maps (per-thread structures). */
- void setRenameMap(RenameMap rm_ptr[O3MaxThreads]);
+ void setRenameMap(UnifiedRenameMap rm_ptr[O3MaxThreads]);
/** Sets pointer to the free list. */
- void setFreeList(FreeList *fl_ptr);
+ void setFreeList(UnifiedFreeList *fl_ptr);
/** Sets pointer to the scoreboard. */
void setScoreboard(Scoreboard *_scoreboard);
@@ -354,10 +353,10 @@
InstQueue skidBuffer[O3MaxThreads];
/** Rename map interface. */
- RenameMap *renameMap[O3MaxThreads];
+ UnifiedRenameMap *renameMap[O3MaxThreads];
/** Free list interface. */
- FreeList *freeList;
+ UnifiedFreeList *freeList;
/** Pointer to the list of active threads. */
std::list<ThreadID> *activeThreads;
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index d8089b9..e4149ee 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -282,7 +282,7 @@
template <class Impl>
void
-DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
+DefaultRename<Impl>::setRenameMap(UnifiedRenameMap rm_ptr[])
{
for (ThreadID tid = 0; tid < numThreads; tid++)
renameMap[tid] = &rm_ptr[tid];
@@ -290,7 +290,7 @@
template <class Impl>
void
-DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
+DefaultRename<Impl>::setFreeList(UnifiedFreeList *fl_ptr)
{
freeList = fl_ptr;
}
@@ -1033,7 +1033,7 @@
DefaultRename<Impl>::renameSrcRegs(const DynInstPtr &inst, ThreadID tid)
{
ThreadContext *tc = inst->tcBase();
- RenameMap *map = renameMap[tid];
+ UnifiedRenameMap *map = renameMap[tid];
unsigned num_src_regs = inst->numSrcRegs();
// Get the architectual register numbers from the source and
@@ -1100,13 +1100,13 @@
DefaultRename<Impl>::renameDestRegs(const DynInstPtr &inst, ThreadID tid)
{
ThreadContext *tc = inst->tcBase();
- RenameMap *map = renameMap[tid];
+ UnifiedRenameMap *map = renameMap[tid];
unsigned num_dest_regs = inst->numDestRegs();
// Rename the destination registers.
for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
const RegId& dest_reg = inst->destRegIdx(dest_idx);
- typename RenameMap::RenameInfo rename_result;
+ UnifiedRenameMap::RenameInfo rename_result;
RegId flat_dest_regid = tc->flattenRegId(dest_reg);
flat_dest_regid.setNumPinnedWrites(dest_reg.getNumPinnedWrites());
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I79c56533cf6a9d1c982cea3ca9bedc83e6afda49
Gerrit-Change-Number: 42099
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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