Alexandru Duțu has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/42215 )
Change subject: sim: Add pool specific allocators to SE mode
......................................................................
sim: Add pool specific allocators to SE mode
The System object supports multiple memory pools but there is currently
no way to specify which pool to allocate from in SE mode. This patch
adds a optional poolID argument to the allocation functions.
Change-Id: I1c732f28905f3b3875adee5f2b0d9abb39a6c5d1
---
M src/sim/system.cc
M src/sim/system.hh
2 files changed, 70 insertions(+), 20 deletions(-)
diff --git a/src/sim/system.cc b/src/sim/system.cc
index bb3c0be..a61358f 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -205,7 +205,6 @@
System::System(const Params &p)
: SimObject(p), _systemPort("system_port", this),
multiThread(p.multi_thread),
- pagePtr(0),
init_param(p.init_param),
physProxy(_systemPort, p.cache_line_size),
workload(p.workload),
@@ -240,6 +239,21 @@
}
#endif
+ AddrRangeList memories = physmem.getConfAddrRanges();
+ assert(!memories.empty());
+ for (const auto &memory : memories) {
+ assert(!memory.interleaved());
+ physMemInfos.emplace_back(memory.start() >> TheISA::PageShift,
+ memory.end() >> TheISA::PageShift);
+ }
+
+ /*
+ * Set pagePtr to what it was before gabe black's page table changes
+ * so allocations don't trample the page table entries.
+ */
+ assert(physMemInfos[0].physFramePtr == 0);
+ physMemInfos[0].physFramePtr = 70;
+
// check if the cache line size is a value known to work
if (!(_cacheLineSize == 16 || _cacheLineSize == 32 ||
_cacheLineSize == 64 || _cacheLineSize == 128))
@@ -374,34 +388,39 @@
}
Addr
-System::allocPhysPages(int npages)
+System::allocPhysPages(int npages, int poolID)
{
- Addr return_addr = pagePtr << TheISA::PageShift;
- pagePtr += npages;
+ Addr &phys_frame = physMemInfos[poolID].physFramePtr;
+ Addr return_addr = phys_frame << TheISA::PageShift;
+ phys_frame += npages;
- Addr next_return_addr = pagePtr << TheISA::PageShift;
+ Addr next_return_addr = phys_frame << TheISA::PageShift;
if (_m5opRange.contains(next_return_addr)) {
warn("Reached m5ops MMIO region\n");
return_addr = 0xffffffff;
- pagePtr = 0xffffffff >> TheISA::PageShift;
+ phys_frame = 0xffffffff >> TheISA::PageShift;
}
- if ((pagePtr << TheISA::PageShift) > physmem.totalSize())
- fatal("Out of memory, please increase size of physical memory.");
+ if (phys_frame > physMemInfos[poolID].physMemLimit) {
+ fatal("Out of memory in pool %d, please increase size of physical "
+ "memory.", poolID);
+ }
+
return return_addr;
}
Addr
-System::memSize() const
+System::memSize(int poolID) const
{
- return physmem.totalSize();
+ return physMemInfos[poolID].physMemLimit << TheISA::PageShift;
}
Addr
-System::freeMemSize() const
+System::freeMemSize(int poolID) const
{
- return physmem.totalSize() - (pagePtr << TheISA::PageShift);
+ return (physMemInfos[poolID].physMemLimit -
+ physMemInfos[poolID].physFramePtr) << TheISA::PageShift;
}
bool
@@ -438,8 +457,6 @@
void
System::serialize(CheckpointOut &cp) const
{
- SERIALIZE_SCALAR(pagePtr);
-
for (auto &t: threads.threads) {
Tick when = 0;
if (t.resumeEvent && t.resumeEvent->scheduled())
@@ -448,6 +465,17 @@
paramOut(cp, csprintf("quiesceEndTick_%d", id), when);
}
+ std::vector<Addr> ptrs;
+ std::vector<Addr> limits;
+
+ for (const auto& memInfo : physMemInfos) {
+ ptrs.push_back(memInfo.physFramePtr);
+ limits.push_back(memInfo.physMemLimit);
+ }
+
+ SERIALIZE_CONTAINER(ptrs);
+ SERIALIZE_CONTAINER(limits);
+
// also serialize the memories in the system
physmem.serializeSection(cp, "physmem");
}
@@ -456,8 +484,6 @@
void
System::unserialize(CheckpointIn &cp)
{
- UNSERIALIZE_SCALAR(pagePtr);
-
for (auto &t: threads.threads) {
Tick when = 0;
ContextID id = t.context->contextId();
@@ -470,6 +496,16 @@
# endif
}
+ std::vector<Addr> ptrs;
+ std::vector<Addr> limits;
+
+ UNSERIALIZE_CONTAINER(ptrs);
+ UNSERIALIZE_CONTAINER(limits);
+
+ assert(ptrs.size() == limits.size());
+ for (size_t i = 0; i < ptrs.size(); i++)
+ physMemInfos.emplace_back(ptrs[i], limits[i]);
+
// also unserialize the memories in the system
physmem.unserializeSection(cp, "physmem");
}
diff --git a/src/sim/system.hh b/src/sim/system.hh
index ce77f0a..f5fc65ee 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -310,7 +310,21 @@
bool schedule(PCEvent *event) override;
bool remove(PCEvent *event) override;
- Addr pagePtr;
+ /** Structure that keeps track of physical frame allocations in SE
mode. */
+ struct PhysMemInfo
+ {
+ /** Current physical frame pointer from which we allocate memory.
*/
+ Addr physFramePtr;
+
+ /** Physical memory limits for this node, in number of frames. */
+ Addr physMemLimit;
+
+ PhysMemInfo(Addr ptr, Addr limit)
+ : physFramePtr(ptr), physMemLimit(limit) { }
+ };
+
+ /** PhysMemInfos for each node */
+ std::vector<PhysMemInfo> physMemInfos;
uint64_t init_param;
@@ -337,10 +351,10 @@
PhysicalMemory& getPhysMem() { return physmem; }
/** Amount of physical memory that is still free */
- Addr freeMemSize() const;
+ Addr freeMemSize(int poolID = 0) const;
/** Amount of physical memory that exists */
- Addr memSize() const;
+ Addr memSize(int poolID = 0) const;
/**
* Check if a physical address is within a range of a memory that
@@ -583,7 +597,7 @@
/// Allocate npages contiguous unused physical pages
/// @return Starting address of first page
- Addr allocPhysPages(int npages);
+ Addr allocPhysPages(int npages, int poolID = 0);
ContextID registerThreadContext(
ThreadContext *tc, ContextID assigned=InvalidContextID);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1c732f28905f3b3875adee5f2b0d9abb39a6c5d1
Gerrit-Change-Number: 42215
Gerrit-PatchSet: 1
Gerrit-Owner: Alexandru Duțu <[email protected]>
Gerrit-CC: Michael LeBeane <[email protected]>
Gerrit-MessageType: newchange
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