Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/42074 )
Change subject: configs, mem: MemInterface generating its own controller
......................................................................
configs, mem: MemInterface generating its own controller
We are adding a controller method to MemInterface objects making
them able to generate the appropriate memory controller.
This will bring the following benefits
a) Semplification: It will simplify MemConfig.config_mem
b) Reusability: Scripts not using config_mem
won't have to duplicate the if...else checks
c) Modularity: Users will be able to define their own
dram interfaces without needing to handle the mem_ctrl
mapping in the shared MemConfig.py module
Change-Id: I4b836fd7c91675cf7aacc644f25989484d5be3ec
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M configs/common/MemConfig.py
M src/mem/DRAMInterface.py
M src/mem/SimpleMemory.py
M src/mem/qos/QoSMemSinkInterface.py
4 files changed, 37 insertions(+), 22 deletions(-)
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 6e78be5..7c32ea7 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2013, 2017, 2020 ARM Limited
+# Copyright (c) 2013, 2017, 2020-2021 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -218,24 +218,7 @@
"latency to 1ns.")
# Create the controller that will drive the interface
- if opt_mem_type == "HMC_2500_1x32":
- # The static latency of the vault controllers is
estimated
- # to be smaller than a full DRAM channel controller
- mem_ctrl = m5.objects.MemCtrl(min_writes_per_switch =
8,
- static_backend_latency
= '4ns',
- static_frontend_latency
= '4ns')
- elif opt_mem_type == "SimpleMemory":
- mem_ctrl = m5.objects.SimpleMemory()
- elif opt_mem_type == "QoSMemSinkInterface":
- mem_ctrl = m5.objects.QoSMemSinkCtrl()
- else:
- mem_ctrl = m5.objects.MemCtrl()
-
- # Hookup the controller to the interface and add to the
list
- if opt_mem_type == "QoSMemSinkInterface":
- mem_ctrl.interface = dram_intf
- elif opt_mem_type != "SimpleMemory":
- mem_ctrl.dram = dram_intf
+ mem_ctrl = dram_intf.controller()
mem_ctrls.append(mem_ctrl)
diff --git a/src/mem/DRAMInterface.py b/src/mem/DRAMInterface.py
index 4f59498..16a4f8b 100644
--- a/src/mem/DRAMInterface.py
+++ b/src/mem/DRAMInterface.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2020 ARM Limited
+# Copyright (c) 2012-2021 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -38,6 +38,7 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+from m5.objects.MemCtrl import MemCtrl
from m5.objects.MemInterface import *
# Enum for the page policy, either open, open_adaptive, close, or
@@ -254,6 +255,15 @@
# Second voltage range defined by some DRAMs
VDD2 = Param.Voltage("0V", "2nd Voltage Range")
+ def controller(self):
+ """
+ Instantiate the memory controller and bind it to
+ the current interface.
+ """
+ controller = MemCtrl()
+ controller.dram = self
+ return controller
+
# A single DDR3-1600 x64 channel (one command and address bus), with
# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
# an 8x8 configuration.
@@ -424,6 +434,15 @@
write_buffer_size = 32
read_buffer_size = 32
+ def controller(self):
+ """
+ Instantiate the memory controller and bind it to
+ the current interface.
+ """
+ return MemCtrl(min_writes_per_switch = 8,
+ static_backend_latency = '4ns',
+ static_frontend_latency = '4ns')
+
# A single DDR3-2133 x64 channel refining a selected subset of the
# options for the DDR-1600 configuration, based on the same DDR3-1600
# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py
index e8eac69..0e059e8 100644
--- a/src/mem/SimpleMemory.py
+++ b/src/mem/SimpleMemory.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013 ARM Limited
+# Copyright (c) 2012-2013, 2021 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -49,3 +49,7 @@
# representative of a x64 DDR3-1600 channel.
bandwidth = Param.MemoryBandwidth('12.8GiB/s',
"Combined read and write bandwidth")
+
+ def controller(self):
+ # Simple memory doesn't use a MemCtrl
+ return self
diff --git a/src/mem/qos/QoSMemSinkInterface.py
b/src/mem/qos/QoSMemSinkInterface.py
index 5c79f64..37ddf78 100644
--- a/src/mem/qos/QoSMemSinkInterface.py
+++ b/src/mem/qos/QoSMemSinkInterface.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2020 ARM Limited
+# Copyright (c) 2020-2021 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -38,3 +38,12 @@
class QoSMemSinkInterface(AbstractMemory):
type = 'QoSMemSinkInterface'
cxx_header = "mem/qos/mem_sink.hh"
+
+ def controller(self):
+ """
+ Instantiate the memory controller and bind it to
+ the current interface.
+ """
+ controller = QoSMemSinkCtrl()
+ controller.interface = self
+ return controller
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4b836fd7c91675cf7aacc644f25989484d5be3ec
Gerrit-Change-Number: 42074
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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