Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41897 )
Change subject: cpu: Remove "lane" accessors from the ExecContext classes.
......................................................................
cpu: Remove "lane" accessors from the ExecContext classes.
These are not used by instructions. If something other than instructions
needs that style of access, it would use the ThreadContext, not the
ExecContext.
Change-Id: Ic74dcfd34f8bb0786bd2688b44d0d90714503637
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41897
Reviewed-by: Gabe Black <gabe.bl...@gmail.com>
Maintainer: Gabe Black <gabe.bl...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/simple/exec_context.hh
5 files changed, 0 insertions(+), 316 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 42a38fc..0900125 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -218,79 +218,6 @@
return thread->getWritableVecReg(reg);
}
- /** Vector Register Lane Interfaces. */
- /** @{ */
- /** Reads source vector 8bit operand. */
- virtual ConstVecLane8
- readVec8BitLaneOperand(const StaticInst *si, int idx) const override
- {
- const RegId& reg = si->destRegIdx(idx);
- assert(reg.isVecReg());
- return thread->readVec8BitLaneReg(reg);
- }
-
- /** Reads source vector 16bit operand. */
- virtual ConstVecLane16
- readVec16BitLaneOperand(const StaticInst *si, int idx) const override
- {
- const RegId& reg = si->destRegIdx(idx);
- assert(reg.isVecReg());
- return thread->readVec16BitLaneReg(reg);
- }
-
- /** Reads source vector 32bit operand. */
- virtual ConstVecLane32
- readVec32BitLaneOperand(const StaticInst *si, int idx) const override
- {
- const RegId& reg = si->destRegIdx(idx);
- assert(reg.isVecReg());
- return thread->readVec32BitLaneReg(reg);
- }
-
- /** Reads source vector 64bit operand. */
- virtual ConstVecLane64
- readVec64BitLaneOperand(const StaticInst *si, int idx) const override
- {
- const RegId& reg = si->destRegIdx(idx);
- assert(reg.isVecReg());
- return thread->readVec64BitLaneReg(reg);
- }
-
- /** Write a lane of the destination vector operand. */
- template <typename LD>
- void
- setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
- {
- const RegId& reg = si->destRegIdx(idx);
- assert(reg.isVecReg());
- return thread->setVecLane(reg, val);
- }
- virtual void
- setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::Byte>& val) override
- {
- setVecLaneOperandT(si, idx, val);
- }
- virtual void
- setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::TwoByte>& val) override
- {
- setVecLaneOperandT(si, idx, val);
- }
- virtual void
- setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::FourByte>& val) override
- {
- setVecLaneOperandT(si, idx, val);
- }
- virtual void
- setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::EightByte>& val) override
- {
- setVecLaneOperandT(si, idx, val);
- }
- /** @} */
-
TheISA::VecElem
readVecElemOperand(const StaticInst *si, int idx) const override
{
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 42dafbc..3c40f31 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -117,36 +117,6 @@
const TheISA::VecRegContainer& val) = 0;
/** @} */
- /** Vector Register Lane Interfaces. */
- /** @{ */
- /** Reads source vector 8bit operand. */
- virtual ConstVecLane8 readVec8BitLaneOperand(
- const StaticInst *si, int idx) const = 0;
-
- /** Reads source vector 16bit operand. */
- virtual ConstVecLane16 readVec16BitLaneOperand(
- const StaticInst *si, int idx) const = 0;
-
- /** Reads source vector 32bit operand. */
- virtual ConstVecLane32 readVec32BitLaneOperand(
- const StaticInst *si, int idx) const = 0;
-
- /** Reads source vector 64bit operand. */
- virtual ConstVecLane64 readVec64BitLaneOperand(
- const StaticInst *si, int idx) const = 0;
-
- /** Write a lane of the destination vector operand. */
- /** @{ */
- virtual void setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::Byte>& val) = 0;
- virtual void setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::TwoByte>& val) = 0;
- virtual void setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::FourByte>& val) = 0;
- virtual void setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::EightByte>& val) = 0;
- /** @} */
-
/** Vector Elem Interfaces. */
/** @{ */
/** Reads an element of a vector register. */
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 153fe29..58f4b4b 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -230,83 +230,6 @@
thread.setVecPredReg(reg, val);
}
- /** Vector Register Lane Interfaces. */
- /** @{ */
- /** Reads source vector 8bit operand. */
- ConstVecLane8
- readVec8BitLaneOperand(const StaticInst *si, int idx) const
- override
- {
- const RegId& reg = si->srcRegIdx(idx);
- assert(reg.isVecReg());
- return thread.readVec8BitLaneReg(reg);
- }
-
- /** Reads source vector 16bit operand. */
- ConstVecLane16
- readVec16BitLaneOperand(const StaticInst *si, int idx) const
- override
- {
- const RegId& reg = si->srcRegIdx(idx);
- assert(reg.isVecReg());
- return thread.readVec16BitLaneReg(reg);
- }
-
- /** Reads source vector 32bit operand. */
- ConstVecLane32
- readVec32BitLaneOperand(const StaticInst *si, int idx) const
- override
- {
- const RegId& reg = si->srcRegIdx(idx);
- assert(reg.isVecReg());
- return thread.readVec32BitLaneReg(reg);
- }
-
- /** Reads source vector 64bit operand. */
- ConstVecLane64
- readVec64BitLaneOperand(const StaticInst *si, int idx) const
- override
- {
- const RegId& reg = si->srcRegIdx(idx);
- assert(reg.isVecReg());
- return thread.readVec64BitLaneReg(reg);
- }
-
- /** Write a lane of the destination vector operand. */
- template <typename LD>
- void
- setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
- {
- const RegId& reg = si->destRegIdx(idx);
- assert(reg.isVecReg());
- return thread.setVecLane(reg, val);
- }
- virtual void
- setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::Byte>& val) override
- {
- setVecLaneOperandT(si, idx, val);
- }
- virtual void
- setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::TwoByte>& val) override
- {
- setVecLaneOperandT(si, idx, val);
- }
- virtual void
- setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::FourByte>& val) override
- {
- setVecLaneOperandT(si, idx, val);
- }
- virtual void
- setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::EightByte>& val) override
- {
- setVecLaneOperandT(si, idx, val);
- }
- /** @} */
-
void
setVecElemOperand(const StaticInst *si, int idx,
const TheISA::VecElem val) override
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 7a54c7f..80eb655 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -268,73 +268,6 @@
return
this->cpu->getWritableVecReg(this->regs.renamedDestIdx(idx));
}
- /** Vector Register Lane Interfaces. */
- /** @{ */
- /** Reads source vector 8bit operand. */
- ConstVecLane8
- readVec8BitLaneOperand(const StaticInst *si, int idx) const override
- {
- return cpu->template readVecLane<uint8_t>(
- this->regs.renamedSrcIdx(idx));
- }
-
- /** Reads source vector 16bit operand. */
- ConstVecLane16
- readVec16BitLaneOperand(const StaticInst *si, int idx) const override
- {
- return cpu->template readVecLane<uint16_t>(
- this->regs.renamedSrcIdx(idx));
- }
-
- /** Reads source vector 32bit operand. */
- ConstVecLane32
- readVec32BitLaneOperand(const StaticInst *si, int idx) const override
- {
- return cpu->template readVecLane<uint32_t>(
- this->regs.renamedSrcIdx(idx));
- }
-
- /** Reads source vector 64bit operand. */
- ConstVecLane64
- readVec64BitLaneOperand(const StaticInst *si, int idx) const override
- {
- return cpu->template readVecLane<uint64_t>(
- this->regs.renamedSrcIdx(idx));
- }
-
- /** Write a lane of the destination vector operand. */
- template <typename LD>
- void
- setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
- {
- return cpu->template setVecLane(this->regs.renamedDestIdx(idx),
val);
- }
- void
- setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::Byte>& val) override
- {
- return setVecLaneOperandT(si, idx, val);
- }
- void
- setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::TwoByte>& val) override
- {
- return setVecLaneOperandT(si, idx, val);
- }
- void
- setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::FourByte>& val) override
- {
- return setVecLaneOperandT(si, idx, val);
- }
- void
- setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::EightByte>& val) override
- {
- return setVecLaneOperandT(si, idx, val);
- }
- /** @} */
-
TheISA::VecElem
readVecElemOperand(const StaticInst *si, int idx) const override
{
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 235c703..218f350 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -344,75 +344,6 @@
thread->setVecReg(reg, val);
}
- /** Vector Register Lane Interfaces. */
- /** @{ */
- /** Reads source vector lane. */
- template <typename VE>
- VecLaneT<VE, true>
- readVecLaneOperand(const StaticInst *si, int idx) const
- {
- execContextStats.numVecRegReads++;
- const RegId& reg = si->srcRegIdx(idx);
- assert(reg.isVecReg());
- return thread->readVecLane<VE>(reg);
- }
- /** Reads source vector 8bit operand. */
- virtual ConstVecLane8
- readVec8BitLaneOperand(const StaticInst *si, int idx) const
- override
- { return readVecLaneOperand<uint8_t>(si, idx); }
-
- /** Reads source vector 16bit operand. */
- virtual ConstVecLane16
- readVec16BitLaneOperand(const StaticInst *si, int idx) const
- override
- { return readVecLaneOperand<uint16_t>(si, idx); }
-
- /** Reads source vector 32bit operand. */
- virtual ConstVecLane32
- readVec32BitLaneOperand(const StaticInst *si, int idx) const
- override
- { return readVecLaneOperand<uint32_t>(si, idx); }
-
- /** Reads source vector 64bit operand. */
- virtual ConstVecLane64
- readVec64BitLaneOperand(const StaticInst *si, int idx) const
- override
- { return readVecLaneOperand<uint64_t>(si, idx); }
-
- /** Write a lane of the destination vector operand. */
- template <typename LD>
- void
- setVecLaneOperandT(const StaticInst *si, int idx,
- const LD& val)
- {
- execContextStats.numVecRegWrites++;
- const RegId& reg = si->destRegIdx(idx);
- assert(reg.isVecReg());
- return thread->setVecLane(reg, val);
- }
- /** Write a lane of the destination vector operand. */
- virtual void
- setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::Byte>& val) override
- { return setVecLaneOperandT(si, idx, val); }
- /** Write a lane of the destination vector operand. */
- virtual void
- setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::TwoByte>& val) override
- { return setVecLaneOperandT(si, idx, val); }
- /** Write a lane of the destination vector operand. */
- virtual void
- setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::FourByte>& val) override
- { return setVecLaneOperandT(si, idx, val); }
- /** Write a lane of the destination vector operand. */
- virtual void
- setVecLaneOperand(const StaticInst *si, int idx,
- const LaneData<LaneSize::EightByte>& val) override
- { return setVecLaneOperandT(si, idx, val); }
- /** @} */
-
/** Reads an element of a vector register. */
TheISA::VecElem
readVecElemOperand(const StaticInst *si, int idx) const override
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41897
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic74dcfd34f8bb0786bd2688b44d0d90714503637
Gerrit-Change-Number: 41897
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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