Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/42350 )
Change subject: arch-x86: Correct style and use uop args in specop.isa.
......................................................................
arch-x86: Correct style and use uop args in specop.isa.
Also spin fixed code out into header files.
Change-Id: I1b326c8cb999d797102ba36b5c13850023a50615
---
M src/arch/x86/insts/microop.hh
M src/arch/x86/insts/microop_args.hh
A src/arch/x86/insts/microspecop.hh
M src/arch/x86/isa/includes.isa
M src/arch/x86/isa/microops/specop.isa
5 files changed, 120 insertions(+), 105 deletions(-)
diff --git a/src/arch/x86/insts/microop.hh b/src/arch/x86/insts/microop.hh
index ac12cec..13c4bee 100644
--- a/src/arch/x86/insts/microop.hh
+++ b/src/arch/x86/insts/microop.hh
@@ -141,6 +141,20 @@
using StaticInst::branchTarget;
};
+class MicroCondBase : public X86MicroopBase
+{
+ protected:
+ uint8_t cc;
+
+ public:
+ MicroCondBase(ExtMachInst mach_inst, const char *mnem,
+ const char *inst_mnem, uint64_t set_flags, OpClass op_class,
+ uint8_t _cc) :
+ X86MicroopBase(mach_inst, mnem, inst_mnem, set_flags, op_class),
+ cc(_cc)
+ {}
+};
+
}
#endif //__ARCH_X86_INSTS_MICROOP_HH__
diff --git a/src/arch/x86/insts/microop_args.hh
b/src/arch/x86/insts/microop_args.hh
index a3ebe29..ac4d81e 100644
--- a/src/arch/x86/insts/microop_args.hh
+++ b/src/arch/x86/insts/microop_args.hh
@@ -37,6 +37,7 @@
#include "arch/x86/types.hh"
#include "base/cprintf.hh"
#include "cpu/reg_class.hh"
+#include "sim/faults.hh"
namespace X86ISA
{
@@ -263,6 +264,22 @@
}
};
+struct FaultOp
+{
+ using ArgType = Fault;
+
+ Fault fault;
+
+ template <class InstType>
+ FaultOp(InstType *inst, ArgType _fault) : fault(_fault) {}
+
+ void
+ print(std::ostream &os) const
+ {
+ ccprintf(os, fault ? fault->name() : "NoFault");
+ }
+};
+
struct AddrOp
{
struct ArgType
diff --git a/src/arch/x86/insts/microspecop.hh
b/src/arch/x86/insts/microspecop.hh
new file mode 100644
index 0000000..e47903c
--- /dev/null
+++ b/src/arch/x86/insts/microspecop.hh
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2021 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_X86_INSTS_MICROSPECOP_HH__
+#define __ARCH_X86_INSTS_MICROSPECOP_HH__
+
+#include "arch/x86/insts/microop.hh"
+#include "cpu/exec_context.hh"
+
+namespace X86ISA
+{
+
+class MicroHalt : public InstOperands<X86MicroopBase>
+{
+ public:
+ MicroHalt(ExtMachInst mach_inst, const char *inst_mnem,
+ uint64_t set_flags) :
+ InstOperands<X86MicroopBase>(mach_inst, "halt", inst_mnem,
+ set_flags | (ULL(1) << StaticInst::IsNonSpeculative) |
+ (ULL(1) << StaticInst::IsQuiesce),
+ No_OpClass)
+ {}
+
+ Fault
+ execute(ExecContext *xc, Trace::InstRecord *) const override
+ {
+ xc->tcBase()->suspend();
+ return NoFault;
+ }
+};
+
+} // namespace X86ISA
+
+#endif //__ARCH_X86_INSTS_MICROSPECOP_HH__
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index b5fedb2..070d82f 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -60,6 +60,7 @@
#include "arch/x86/insts/microldstop.hh"
#include "arch/x86/insts/micromediaop.hh"
#include "arch/x86/insts/microregop.hh"
+#include "arch/x86/insts/microspecop.hh"
#include "arch/x86/insts/static_inst.hh"
#include "arch/x86/isa_traits.hh"
#include "arch/x86/registers.hh"
diff --git a/src/arch/x86/isa/microops/specop.isa
b/src/arch/x86/isa/microops/specop.isa
index aad171a..c5fe5bc 100644
--- a/src/arch/x86/isa/microops/specop.isa
+++ b/src/arch/x86/isa/microops/specop.isa
@@ -40,40 +40,6 @@
//
//////////////////////////////////////////////////////////////////////////
-output header {{
- class MicroFaultBase : public X86ISA::X86MicroopBase
- {
- protected:
- Fault fault;
- uint8_t cc;
-
- public:
- MicroFaultBase(ExtMachInst _machInst, const char * instMnem,
- uint64_t setFlags, Fault _fault, uint8_t _cc);
-
- std::string generateDisassembly(Addr pc,
- const Loader::SymbolTable *symtab) const override;
- };
-
- class MicroHalt : public X86ISA::X86MicroopBase
- {
- public:
- MicroHalt(ExtMachInst _machInst, const char * instMnem,
- uint64_t setFlags) :
- X86MicroopBase(_machInst, "halt", instMnem,
- setFlags | (ULL(1) <<
StaticInst::IsNonSpeculative) |
- (ULL(1) << StaticInst::IsQuiesce),
- No_OpClass)
- {
- }
-
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
-
- std::string generateDisassembly(Addr pc,
- const Loader::SymbolTable *symtab) const override;
- };
-}};
-
def template MicroFaultDeclare {{
class %(class_name)s : public %(base_class)s
{
@@ -81,86 +47,41 @@
%(reg_idx_arr_decl)s;
public:
- %(class_name)s(ExtMachInst _machInst, const char * instMnem,
- uint64_t setFlags, Fault _fault, uint8_t _cc);
+ %(class_name)s(ExtMachInst mach_inst, const char *inst_mnem,
+ uint64_t set_flags, Fault _fault, uint8_t _cc);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template MicroFaultExecute {{
- Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- %(op_decl)s;
- %(op_rd)s;
- if (%(cond_test)s) {
- //Return the fault we were constructed with
- return fault;
- } else {
- return NoFault;
- }
- }
-}};
-
-output exec {{
Fault
- MicroHalt::execute(ExecContext *xc, Trace::InstRecord * traceData)
const
+ %(class_name)s::execute(ExecContext *xc,
+ Trace::InstRecord *traceData) const
{
- xc->tcBase()->suspend();
- return NoFault;
- }
-}};
-
-output decoder {{
- MicroFaultBase::MicroFaultBase(
- ExtMachInst machInst, const char * instMnem,
- uint64_t setFlags, Fault _fault, uint8_t _cc) :
- X86MicroopBase(machInst, "fault", instMnem, setFlags, No_OpClass),
- fault(_fault), cc(_cc)
- {
+ %(op_decl)s;
+ %(op_rd)s;
+ if (%(cond_test)s) {
+ // Return the fault we were constructed with.
+ return fault;
+ } else {
+ return NoFault;
+ }
}
}};
def template MicroFaultConstructor {{
%(class_name)s::%(class_name)s(
- ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
+ ExtMachInst mach_inst, const char *inst_mnem, uint64_t
set_flags,
Fault _fault, uint8_t _cc) :
- %(base_class)s(machInst, instMnem, setFlags, _fault, _cc)
+ %(base_class)s(mach_inst, "fault", inst_mnem, set_flags,
No_OpClass,
+ _fault, _cc)
{
%(set_reg_idx_arr)s;
%(constructor)s;
}
}};
-output decoder {{
- std::string
- MicroFaultBase::generateDisassembly(
- Addr pc, const Loader::SymbolTable *symtab) const
- {
- std::stringstream response;
-
- printMnemonic(response, instMnem, mnemonic);
- if(fault)
- response << fault->name();
- else
- response << "No Fault";
-
- return response.str();
- }
-
- std::string
- MicroHalt::generateDisassembly(
- Addr pc, const Loader::SymbolTable *symtab) const
- {
- std::stringstream response;
-
- printMnemonic(response, instMnem, mnemonic);
-
- return response.str();
- }
-}};
-
let {{
class Fault(X86Microop):
className = "MicroFault"
@@ -183,14 +104,16 @@
"cc" : self.cond}
return allocator
- iop = InstObjParams("fault", "MicroFaultFlags", "MicroFaultBase",
+ iop = InstObjParams("fault", "MicroFaultFlags",
+ "X86ISA::InstOperands<X86ISA::MicroCondBase, X86ISA::FaultOp>",
{"code": "",
"cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
ecfBit | ezfBit, cc)"})
exec_output = MicroFaultExecute.subst(iop)
header_output = MicroFaultDeclare.subst(iop)
decoder_output = MicroFaultConstructor.subst(iop)
- iop = InstObjParams("fault", "MicroFault", "MicroFaultBase",
+ iop = InstObjParams("fault", "MicroFault",
+ "X86ISA::InstOperands<X86ISA::MicroCondBase, X86ISA::FaultOp>",
{"code": "",
"cond_test": "true"})
exec_output += MicroFaultExecute.subst(iop)
@@ -204,7 +127,7 @@
pass
def getAllocator(self, microFlags):
- return "new MicroHalt(machInst, macrocodeBlock, %s)" % \
+ return "new X86ISA::MicroHalt(machInst, macrocodeBlock, %s)" %
\
self.microFlagsText(microFlags)
microopClasses["halt"] = Halt
@@ -217,19 +140,22 @@
%(reg_idx_arr_decl)s;
public:
- %(class_name)s(ExtMachInst _machInst,
- const char * instMnem,
- uint64_t setFlags);
+ %(class_name)s(ExtMachInst mach_inst, const char *inst_mnem,
+ uint64_t set_flags);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault
+ execute(ExecContext *, Trace::InstRecord *) const override
+ {
+ return NoFault;
+ }
};
}};
def template MicroFenceOpConstructor {{
%(class_name)s::%(class_name)s(
- ExtMachInst machInst, const char * instMnem, uint64_t
setFlags) :
- %(base_class)s(machInst, "%(mnemonic)s", instMnem,
- setFlags, %(op_class)s)
+ ExtMachInst mach_inst, const char *inst_mnem, uint64_t
set_flags) :
+ %(base_class)s(mach_inst, "%(mnemonic)s", inst_mnem,
+ set_flags, %(op_class)s)
{
%(set_reg_idx_arr)s;
%(constructor)s;
@@ -264,5 +190,4 @@
{"code" : ""})
header_output += MicroFenceOpDeclare.subst(iop)
decoder_output += MicroFenceOpConstructor.subst(iop)
- exec_output += BasicExecute.subst(iop)
}};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1b326c8cb999d797102ba36b5c13850023a50615
Gerrit-Change-Number: 42350
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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