Hey folks, and particular ARM folks. I have a series of CLs that I just uploaded which rework how operands are laid out in x86 microops. The problem it addresses is that many microops take slightly different operands (no destiation for comparisons, maybe only one source, floating point vs integer registers, etc), and so there can be an explosion of base classes to cover all those possibilities and track all those different combinations of operands.
On x86, this was "handled" by having a relatively small number of classe and relatively conforming microops, but then just jamming them together where they didn't quite fit. Need three sources? Re-use a destination as a source. Need to destinations? Repurpose a source as a destination. Don't need both sources? Set one to the zero register. Instead, this will now be handled through modularized base classes based on templates where you can mix and match any combination of operands you want after the fact without having to explicitly define classes for each combination. Also, as a nice bonus, clean, accurate disassembly methods are now automatically generated, and all the operands for all the microops have type checking. You can't specify an integer register where a floating point one is expected, you can't specify the actual miscreg index for a control register when the number of the register itself (cr0 vs cr3, etc) is expected, etc. On ARM, this was handled, I think, by having approximately 100,000 base classes with all the possible combinations of operands. I'm not quite comfortable enough with ARM to jump in there and implement this same system there, but it would be quite possible based on the example I did in X86, and I think would clean up the ARM implementation quite a bit. Let me know if you're interested and/or have questions about how it works and could be applied to ARM. https://gem5-review.googlesource.com/c/public/gem5/+/42362 Gabe
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