Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/43328 )
Change subject: misc: Fix coding style for union's opening braces
......................................................................
misc: Fix coding style for union's opening braces
The systemc dir was not included in this fix.
First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation, using:
grep -nrE --exclude-dir=systemc \
"^ *union [A-Za-z].* {$" src/
Then the following commands were run to replace:
<indent level>union X ... {
by:
<indent level>union X ...
<indent level>{
Level 0:
grep -nrl --exclude-dir=systemc \
"^union [A-Za-z].* {$" src/ | \
xargs sed -Ei \
's/^union ([A-Za-z].*) \{$/union \1\n\{/g'
Level 1:
grep -nrl --exclude-dir=systemc \
"^ union [A-Za-z].* {$" src/ | \
xargs sed -Ei \
's/^ union ([A-Za-z].*) \{$/ union \1\n \{/g'
and so on.
Change-Id: I066854eb27a8acd2cc2dfa41596bb1b1f66c71b1
Signed-off-by: Daniel R. Carvalho <oda...@yahoo.com.br>
---
M src/arch/arm/isa/insts/macromem.isa
M src/arch/arm/isa/insts/neon64_mem.isa
M src/arch/arm/kvm/armv8_cpu.cc
M src/arch/gcn3/gpu_decoder.hh
M src/cpu/inst_res.hh
M src/dev/pci/pcireg.h
M src/sim/syscall_emul.cc
7 files changed, 38 insertions(+), 19 deletions(-)
diff --git a/src/arch/arm/isa/insts/macromem.isa
b/src/arch/arm/isa/insts/macromem.isa
index f9f6e72..94acf41 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -194,7 +194,8 @@
regs = (size + 3) // 4
subst = { "size" : size, "regs" : regs }
memDecl = '''
- union MemUnion {
+ union MemUnion
+ {
uint8_t bytes[%(size)d];
Element elements[%(size)d / sizeof(Element)];
uint32_t floatRegBits[%(regs)d];
@@ -312,7 +313,8 @@
const unsigned regs = 2 * dRegs;
const unsigned perDReg =
(2 * sizeof(uint32_t)) / sizeof(Element);
- union convStruct {
+ union convStruct
+ {
uint32_t cRegs[regs];
Element elements[dRegs * perDReg];
} conv1, conv2;
@@ -358,7 +360,8 @@
const unsigned regs = 2 * dRegs;
const unsigned perDReg =
(2 * sizeof(uint32_t)) / sizeof(Element);
- union convStruct {
+ union convStruct
+ {
uint32_t cRegs[regs];
Element elements[dRegs * perDReg];
} conv1, conv2;
@@ -431,12 +434,14 @@
microUnpackNeonCode = '''
const unsigned perDReg = (2 * sizeof(uint32_t)) /
sizeof(Element);
- union SourceRegs {
+ union SourceRegs
+ {
uint32_t fRegs[2 * %(sRegs)d];
Element elements[%(sRegs)d * perDReg];
} sourceRegs;
- union DestReg {
+ union DestReg
+ {
uint32_t fRegs[2];
Element elements[perDReg];
} destRegs[%(dRegs)d];
@@ -479,12 +484,14 @@
microUnpackAllNeonCode = '''
const unsigned perDReg = (2 * sizeof(uint32_t)) /
sizeof(Element);
- union SourceRegs {
+ union SourceRegs
+ {
uint32_t fRegs[2 * %(sRegs)d];
Element elements[%(sRegs)d * perDReg];
} sourceRegs;
- union DestReg {
+ union DestReg
+ {
uint32_t fRegs[2];
Element elements[perDReg];
} destRegs[%(dRegs)d];
@@ -529,12 +536,14 @@
const unsigned perDReg =
(2 * sizeof(uint32_t)) / sizeof(Element);
- union SourceReg {
+ union SourceReg
+ {
uint32_t fRegs[2];
Element elements[perDReg];
} sourceRegs[%(sRegs)d];
- union DestRegs {
+ union DestRegs
+ {
uint32_t fRegs[2 * %(dRegs)d];
Element elements[%(dRegs)d * perDReg];
} destRegs;
diff --git a/src/arch/arm/isa/insts/neon64_mem.isa
b/src/arch/arm/isa/insts/neon64_mem.isa
index 4977c41..d1c21d1 100644
--- a/src/arch/arm/isa/insts/neon64_mem.isa
+++ b/src/arch/arm/isa/insts/neon64_mem.isa
@@ -59,7 +59,8 @@
'''
memDecl = '''
const int MaxNumBytes = 16;
- union MemUnion {
+ union MemUnion
+ {
uint8_t bytes[MaxNumBytes];
uint32_t floatRegBits[MaxNumBytes / 4];
};
diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index 54fa8b2..94dd093 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -81,7 +81,8 @@
(SIMD_REG(fp_regs.vregs[1]) - SIMD_REG(fp_regs.vregs[0])) * num;
}
-union KvmFPReg {
+union KvmFPReg
+{
union {
uint32_t i;
float f;
diff --git a/src/arch/gcn3/gpu_decoder.hh b/src/arch/gcn3/gpu_decoder.hh
index b9ae136..0cd668b 100644
--- a/src/arch/gcn3/gpu_decoder.hh
+++ b/src/arch/gcn3/gpu_decoder.hh
@@ -1635,7 +1635,8 @@
unsigned int SRC1_ABS : 1;
};
- union InstFormat {
+ union InstFormat
+ {
InFmt_DS iFmt_DS;
InFmt_DS_1 iFmt_DS_1;
InFmt_EXP iFmt_EXP;
diff --git a/src/cpu/inst_res.hh b/src/cpu/inst_res.hh
index 0495138..21ed297 100644
--- a/src/cpu/inst_res.hh
+++ b/src/cpu/inst_res.hh
@@ -46,7 +46,8 @@
class InstResult
{
public:
- union MultiResult {
+ union MultiResult
+ {
uint64_t integer;
double dbl;
TheISA::VecRegContainer vector;
diff --git a/src/dev/pci/pcireg.h b/src/dev/pci/pcireg.h
index 67d5a61..8341ee4 100644
--- a/src/dev/pci/pcireg.h
+++ b/src/dev/pci/pcireg.h
@@ -64,7 +64,8 @@
Bitfield<0> ioSpace;
EndBitUnion(PciCommandRegister)
-union PCIConfig {
+union PCIConfig
+{
uint8_t data[64];
struct {
@@ -216,7 +217,8 @@
* Defines the Power Management capability register and all its associated
* bitfields for a PCIe device.
*/
-union PMCAP {
+union PMCAP
+{
uint8_t data[6];
struct {
uint16_t pid; /* 0:7 cid
@@ -249,7 +251,8 @@
* can be filled in if a device model supports both, but only 1 of
* MSI/MSIX/INTx interrupt mode can be selected at a given time.
*/
-union MSICAP {
+union MSICAP
+{
uint8_t data[24];
struct {
uint16_t mid; /* 0:7 cid
@@ -276,7 +279,8 @@
* Defines the MSI-X Capability register and its associated bitfields for
* a PCIe device.
*/
-union MSIXCAP {
+union MSIXCAP
+{
uint8_t data[12];
struct {
uint16_t mxid; /* 0:7 cid
@@ -296,7 +300,8 @@
};
};
-union MSIXTable {
+union MSIXTable
+{
struct {
uint32_t addr_lo;
uint32_t addr_hi;
diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
index 4f6716b..6618ebf 100644
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -1517,7 +1517,8 @@
VPtr<> lenPtr)
{
// union of all possible return value types from getsockopt
- union val {
+ union val
+ {
int i_val;
long l_val;
struct linger linger_val;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/43328
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I066854eb27a8acd2cc2dfa41596bb1b1f66c71b1
Gerrit-Change-Number: 43328
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
