Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41739 )
Change subject: arch-mips: Pull non-public values out of registers.hh.
......................................................................
arch-mips: Pull non-public values out of registers.hh.
Change-Id: Ia15c75547e74bf2f784fac5b3063159e0c79a00c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41739
Maintainer: Bobby R. Bruce <bbr...@ucdavis.edu>
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Gabe Black <gabe.bl...@gmail.com>
---
M src/arch/mips/faults.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/mips/isa/includes.isa
M src/arch/mips/linux/se_workload.cc
M src/arch/mips/locked_mem.hh
M src/arch/mips/mt.hh
M src/arch/mips/process.cc
M src/arch/mips/registers.hh
A src/arch/mips/regs/float.hh
A src/arch/mips/regs/int.hh
A src/arch/mips/regs/misc.hh
M src/arch/mips/remote_gdb.cc
M src/arch/mips/remote_gdb.hh
M src/arch/mips/se_workload.hh
M src/arch/mips/utility.cc
M src/arch/mips/utility.hh
17 files changed, 369 insertions(+), 234 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 6352601..9875ab6 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -31,6 +31,7 @@
#define __MIPS_FAULTS_HH__
#include "arch/mips/pra_constants.hh"
+#include "arch/mips/regs/misc.hh"
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
#include "sim/faults.hh"
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 46116c2..11d2e80 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -31,6 +31,9 @@
#include "arch/mips/mt.hh"
#include "arch/mips/mt_constants.hh"
#include "arch/mips/pra_constants.hh"
+#include "arch/mips/regs/float.hh"
+#include "arch/mips/regs/int.hh"
+#include "arch/mips/regs/misc.hh"
#include "base/bitfield.hh"
#include "cpu/base.hh"
#include "cpu/reg_class.hh"
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index e5778d3..490008c 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -34,15 +34,15 @@
#include <vector>
#include "arch/generic/isa.hh"
-#include "arch/mips/registers.hh"
+#include "arch/mips/regs/misc.hh"
#include "arch/mips/types.hh"
+#include "base/types.hh"
#include "cpu/reg_class.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
class BaseCPU;
class Checkpoint;
-class EventManager;
struct MipsISAParams;
class ThreadContext;
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 48b0a10..8ee2877 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -53,6 +53,9 @@
#include "arch/mips/mt_constants.hh"
#include "arch/mips/pagetable.hh"
#include "arch/mips/pra_constants.hh"
+#include "arch/mips/regs/float.hh"
+#include "arch/mips/regs/int.hh"
+#include "arch/mips/regs/misc.hh"
#include "arch/mips/tlb.hh"
#include "arch/mips/utility.hh"
#include "base/cprintf.hh"
@@ -76,6 +79,9 @@
#include "arch/mips/mt_constants.hh"
#include "arch/mips/pagetable.hh"
#include "arch/mips/pra_constants.hh"
+#include "arch/mips/regs/float.hh"
+#include "arch/mips/regs/int.hh"
+#include "arch/mips/regs/misc.hh"
#include "arch/mips/tlb.hh"
#include "arch/mips/utility.hh"
#include "base/condcodes.hh"
diff --git a/src/arch/mips/linux/se_workload.cc
b/src/arch/mips/linux/se_workload.cc
index ef12f4f..2edb764 100644
--- a/src/arch/mips/linux/se_workload.cc
+++ b/src/arch/mips/linux/se_workload.cc
@@ -32,6 +32,7 @@
#include <sys/syscall.h>
#include "arch/mips/process.hh"
+#include "arch/mips/regs/misc.hh"
#include "base/loader/object_file.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 73180af..42a4ed2 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -47,7 +47,7 @@
* ISA-specific helper functions for locked memory accesses.
*/
-#include "arch/mips/registers.hh"
+#include "arch/mips/regs/misc.hh"
#include "base/logging.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index c42cd9a..ae4ed97 100644
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -40,7 +40,7 @@
#include "arch/mips/faults.hh"
#include "arch/mips/mt_constants.hh"
#include "arch/mips/pra_constants.hh"
-#include "arch/mips/registers.hh"
+#include "arch/mips/regs/misc.hh"
#include "base/bitfield.hh"
#include "base/logging.hh"
#include "base/trace.hh"
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index ccabd3f..9810d67 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -29,6 +29,7 @@
#include "arch/mips/process.hh"
#include "arch/mips/page_size.hh"
+#include "arch/mips/regs/int.hh"
#include "base/loader/elf_object.hh"
#include "base/loader/object_file.hh"
#include "base/logging.hh"
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 9d38f31..1f49262 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -32,238 +32,11 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-#include "base/logging.hh"
-#include "base/types.hh"
-
-class ThreadContext;
namespace MipsISA
{
-// Constants Related to the number of registers
-const int NumIntArchRegs = 32;
-const int NumIntSpecialRegs = 9;
-const int NumFloatArchRegs = 32;
-const int NumFloatSpecialRegs = 5;
-
-const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
-const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI &
LO Regs
-const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
-
-const uint32_t MIPS32_QNAN = 0x7fbfffff;
-const uint64_t MIPS64_QNAN = 0x7ff7ffffffffffffULL;
-
-enum FPControlRegNums
-{
- FLOATREG_FIR = NumFloatArchRegs,
- FLOATREG_FCCR,
- FLOATREG_FEXR,
- FLOATREG_FENR,
- FLOATREG_FCSR
-};
-
-enum FCSRBits
-{
- Inexact = 1,
- Underflow,
- Overflow,
- DivideByZero,
- Invalid,
- Unimplemented
-};
-
-enum FCSRFields
-{
- Flag_Field = 1,
- Enable_Field = 6,
- Cause_Field = 11
-};
-
-enum MiscIntRegNums
-{
- INTREG_LO = NumIntArchRegs,
- INTREG_DSP_LO0 = INTREG_LO,
- INTREG_HI,
- INTREG_DSP_HI0 = INTREG_HI,
- INTREG_DSP_ACX0,
- INTREG_DSP_LO1,
- INTREG_DSP_HI1,
- INTREG_DSP_ACX1,
- INTREG_DSP_LO2,
- INTREG_DSP_HI2,
- INTREG_DSP_ACX2,
- INTREG_DSP_LO3,
- INTREG_DSP_HI3,
- INTREG_DSP_ACX3,
- INTREG_DSP_CONTROL
-};
-
-// semantically meaningful register indices
const int ZeroReg = 0;
-const int SyscallSuccessReg = 7;
-const int FirstArgumentReg = 4;
-const int ReturnValueReg = 2;
-
-const int StackPointerReg = 29;
-
-const int SyscallPseudoReturnReg = 3;
-
-// Enumerate names for 'Control' Registers in the CPU
-// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
-// (Register Number-Register Select) Summary of Register
-//------------------------------------------------------
-// The first set of names classify the CP0 names as Register Banks
-// for easy indexing when using the 'RD + SEL' index combination
-// in CP0 instructions.
-enum MiscRegIndex{
- MISCREG_INDEX = 0, //Bank 0: 0 - 3
- MISCREG_MVP_CONTROL,
- MISCREG_MVP_CONF0,
- MISCREG_MVP_CONF1,
-
- MISCREG_CP0_RANDOM = 8, //Bank 1: 8 - 15
- MISCREG_VPE_CONTROL,
- MISCREG_VPE_CONF0,
- MISCREG_VPE_CONF1,
- MISCREG_YQMASK,
- MISCREG_VPE_SCHEDULE,
- MISCREG_VPE_SCHEFBACK,
- MISCREG_VPE_OPT,
-
- MISCREG_ENTRYLO0 = 16, //Bank 2: 16 - 23
- MISCREG_TC_STATUS,
- MISCREG_TC_BIND,
- MISCREG_TC_RESTART,
- MISCREG_TC_HALT,
- MISCREG_TC_CONTEXT,
- MISCREG_TC_SCHEDULE,
- MISCREG_TC_SCHEFBACK,
-
- MISCREG_ENTRYLO1 = 24, // Bank 3: 24
-
- MISCREG_CONTEXT = 32, // Bank 4: 32 - 33
- MISCREG_CONTEXT_CONFIG,
-
- MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41
- MISCREG_PAGEGRAIN = 41,
-
- MISCREG_WIRED = 48, //Bank 6:48-55
- MISCREG_SRS_CONF0,
- MISCREG_SRS_CONF1,
- MISCREG_SRS_CONF2,
- MISCREG_SRS_CONF3,
- MISCREG_SRS_CONF4,
-
- MISCREG_HWRENA = 56, //Bank 7: 56-63
-
- MISCREG_BADVADDR = 64, //Bank 8: 64-71
-
- MISCREG_COUNT = 72, //Bank 9: 72-79
-
- MISCREG_ENTRYHI = 80, //Bank 10: 80-87
-
- MISCREG_COMPARE = 88, //Bank 11: 88-95
-
- MISCREG_STATUS = 96, //Bank 12: 96-103
- MISCREG_INTCTL,
- MISCREG_SRSCTL,
- MISCREG_SRSMAP,
-
- MISCREG_CAUSE = 104, //Bank 13: 104-111
-
- MISCREG_EPC = 112, //Bank 14: 112-119
-
- MISCREG_PRID = 120, //Bank 15: 120-127,
- MISCREG_EBASE,
-
- MISCREG_CONFIG = 128, //Bank 16: 128-135
- MISCREG_CONFIG1,
- MISCREG_CONFIG2,
- MISCREG_CONFIG3,
- MISCREG_CONFIG4,
- MISCREG_CONFIG5,
- MISCREG_CONFIG6,
- MISCREG_CONFIG7,
-
-
- MISCREG_LLADDR = 136, //Bank 17: 136-143
-
- MISCREG_WATCHLO0 = 144, //Bank 18: 144-151
- MISCREG_WATCHLO1,
- MISCREG_WATCHLO2,
- MISCREG_WATCHLO3,
- MISCREG_WATCHLO4,
- MISCREG_WATCHLO5,
- MISCREG_WATCHLO6,
- MISCREG_WATCHLO7,
-
- MISCREG_WATCHHI0 = 152, //Bank 19: 152-159
- MISCREG_WATCHHI1,
- MISCREG_WATCHHI2,
- MISCREG_WATCHHI3,
- MISCREG_WATCHHI4,
- MISCREG_WATCHHI5,
- MISCREG_WATCHHI6,
- MISCREG_WATCHHI7,
-
- MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
-
- //Bank 21: 168-175
-
- //Bank 22: 176-183
-
- MISCREG_DEBUG = 184, //Bank 23: 184-191
- MISCREG_TRACE_CONTROL1,
- MISCREG_TRACE_CONTROL2,
- MISCREG_USER_TRACE_DATA,
- MISCREG_TRACE_BPC,
-
- MISCREG_DEPC = 192, //Bank 24: 192-199
-
- MISCREG_PERFCNT0 = 200, //Bank 25: 200-207
- MISCREG_PERFCNT1,
- MISCREG_PERFCNT2,
- MISCREG_PERFCNT3,
- MISCREG_PERFCNT4,
- MISCREG_PERFCNT5,
- MISCREG_PERFCNT6,
- MISCREG_PERFCNT7,
-
- MISCREG_ERRCTL = 208, //Bank 26: 208-215
-
- MISCREG_CACHEERR0 = 216, //Bank 27: 216-223
- MISCREG_CACHEERR1,
- MISCREG_CACHEERR2,
- MISCREG_CACHEERR3,
-
- MISCREG_TAGLO0 = 224, //Bank 28: 224-231
- MISCREG_DATALO1,
- MISCREG_TAGLO2,
- MISCREG_DATALO3,
- MISCREG_TAGLO4,
- MISCREG_DATALO5,
- MISCREG_TAGLO6,
- MISCREG_DATALO7,
-
- MISCREG_TAGHI0 = 232, //Bank 29: 232-239
- MISCREG_DATAHI1,
- MISCREG_TAGHI2,
- MISCREG_DATAHI3,
- MISCREG_TAGHI4,
- MISCREG_DATAHI5,
- MISCREG_TAGHI6,
- MISCREG_DATAHI7,
-
-
- MISCREG_ERROR_EPC = 240, //Bank 30: 240-247
-
- MISCREG_DESAVE = 248, //Bank 31: 248-256
-
- MISCREG_LLFLAG = 257,
- MISCREG_TP_VALUE,
-
- MISCREG_NUMREGS
-};
// Not applicable to MIPS
using VecElem = ::DummyVecElem;
diff --git a/src/arch/mips/regs/float.hh b/src/arch/mips/regs/float.hh
new file mode 100644
index 0000000..8a0769f
--- /dev/null
+++ b/src/arch/mips/regs/float.hh
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_MIPS_REGS_FLOAT_HH__
+#define __ARCH_MIPS_REGS_FLOAT_HH__
+
+#include <cstdint>
+
+namespace MipsISA
+{
+
+// Constants Related to the number of registers
+const int NumFloatArchRegs = 32;
+const int NumFloatSpecialRegs = 5;
+
+const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
+
+const uint32_t MIPS32_QNAN = 0x7fbfffff;
+const uint64_t MIPS64_QNAN = 0x7ff7ffffffffffffULL;
+
+enum FPControlRegNums
+{
+ FLOATREG_FIR = NumFloatArchRegs,
+ FLOATREG_FCCR,
+ FLOATREG_FEXR,
+ FLOATREG_FENR,
+ FLOATREG_FCSR
+};
+
+enum FCSRBits
+{
+ Inexact = 1,
+ Underflow,
+ Overflow,
+ DivideByZero,
+ Invalid,
+ Unimplemented
+};
+
+enum FCSRFields
+{
+ Flag_Field = 1,
+ Enable_Field = 6,
+ Cause_Field = 11
+};
+
+} // namespace MipsISA
+
+#endif
diff --git a/src/arch/mips/regs/int.hh b/src/arch/mips/regs/int.hh
new file mode 100644
index 0000000..0d0f35d
--- /dev/null
+++ b/src/arch/mips/regs/int.hh
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_MIPS_REGS_INT_HH__
+#define __ARCH_MIPS_REGS_INT_HH__
+
+namespace MipsISA
+{
+
+// Constants Related to the number of registers
+const int NumIntArchRegs = 32;
+const int NumIntSpecialRegs = 9;
+
+const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
+const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
+
+enum MiscIntRegNums
+{
+ INTREG_LO = NumIntArchRegs,
+ INTREG_DSP_LO0 = INTREG_LO,
+ INTREG_HI,
+ INTREG_DSP_HI0 = INTREG_HI,
+ INTREG_DSP_ACX0,
+ INTREG_DSP_LO1,
+ INTREG_DSP_HI1,
+ INTREG_DSP_ACX1,
+ INTREG_DSP_LO2,
+ INTREG_DSP_HI2,
+ INTREG_DSP_ACX2,
+ INTREG_DSP_LO3,
+ INTREG_DSP_HI3,
+ INTREG_DSP_ACX3,
+ INTREG_DSP_CONTROL
+};
+
+// semantically meaningful register indices
+const int SyscallSuccessReg = 7;
+const int FirstArgumentReg = 4;
+const int ReturnValueReg = 2;
+
+const int StackPointerReg = 29;
+
+const int SyscallPseudoReturnReg = 3;
+
+} // namespace MipsISA
+
+#endif
diff --git a/src/arch/mips/regs/misc.hh b/src/arch/mips/regs/misc.hh
new file mode 100644
index 0000000..c3df37e
--- /dev/null
+++ b/src/arch/mips/regs/misc.hh
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_MIPS_REGS_MISC_HH__
+#define __ARCH_MIPS_REGS_MISC_HH__
+
+namespace MipsISA
+{
+
+// Enumerate names for 'Control' Registers in the CPU
+// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
+// (Register Number-Register Select) Summary of Register
+//------------------------------------------------------
+// The first set of names classify the CP0 names as Register Banks
+// for easy indexing when using the 'RD + SEL' index combination
+// in CP0 instructions.
+enum MiscRegIndex
+{
+ MISCREG_INDEX = 0, //Bank 0: 0 - 3
+ MISCREG_MVP_CONTROL,
+ MISCREG_MVP_CONF0,
+ MISCREG_MVP_CONF1,
+
+ MISCREG_CP0_RANDOM = 8, //Bank 1: 8 - 15
+ MISCREG_VPE_CONTROL,
+ MISCREG_VPE_CONF0,
+ MISCREG_VPE_CONF1,
+ MISCREG_YQMASK,
+ MISCREG_VPE_SCHEDULE,
+ MISCREG_VPE_SCHEFBACK,
+ MISCREG_VPE_OPT,
+
+ MISCREG_ENTRYLO0 = 16, //Bank 2: 16 - 23
+ MISCREG_TC_STATUS,
+ MISCREG_TC_BIND,
+ MISCREG_TC_RESTART,
+ MISCREG_TC_HALT,
+ MISCREG_TC_CONTEXT,
+ MISCREG_TC_SCHEDULE,
+ MISCREG_TC_SCHEFBACK,
+
+ MISCREG_ENTRYLO1 = 24, // Bank 3: 24
+
+ MISCREG_CONTEXT = 32, // Bank 4: 32 - 33
+ MISCREG_CONTEXT_CONFIG,
+
+ MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41
+ MISCREG_PAGEGRAIN = 41,
+
+ MISCREG_WIRED = 48, //Bank 6:48-55
+ MISCREG_SRS_CONF0,
+ MISCREG_SRS_CONF1,
+ MISCREG_SRS_CONF2,
+ MISCREG_SRS_CONF3,
+ MISCREG_SRS_CONF4,
+
+ MISCREG_HWRENA = 56, //Bank 7: 56-63
+
+ MISCREG_BADVADDR = 64, //Bank 8: 64-71
+
+ MISCREG_COUNT = 72, //Bank 9: 72-79
+
+ MISCREG_ENTRYHI = 80, //Bank 10: 80-87
+
+ MISCREG_COMPARE = 88, //Bank 11: 88-95
+
+ MISCREG_STATUS = 96, //Bank 12: 96-103
+ MISCREG_INTCTL,
+ MISCREG_SRSCTL,
+ MISCREG_SRSMAP,
+
+ MISCREG_CAUSE = 104, //Bank 13: 104-111
+
+ MISCREG_EPC = 112, //Bank 14: 112-119
+
+ MISCREG_PRID = 120, //Bank 15: 120-127,
+ MISCREG_EBASE,
+
+ MISCREG_CONFIG = 128, //Bank 16: 128-135
+ MISCREG_CONFIG1,
+ MISCREG_CONFIG2,
+ MISCREG_CONFIG3,
+ MISCREG_CONFIG4,
+ MISCREG_CONFIG5,
+ MISCREG_CONFIG6,
+ MISCREG_CONFIG7,
+
+
+ MISCREG_LLADDR = 136, //Bank 17: 136-143
+
+ MISCREG_WATCHLO0 = 144, //Bank 18: 144-151
+ MISCREG_WATCHLO1,
+ MISCREG_WATCHLO2,
+ MISCREG_WATCHLO3,
+ MISCREG_WATCHLO4,
+ MISCREG_WATCHLO5,
+ MISCREG_WATCHLO6,
+ MISCREG_WATCHLO7,
+
+ MISCREG_WATCHHI0 = 152, //Bank 19: 152-159
+ MISCREG_WATCHHI1,
+ MISCREG_WATCHHI2,
+ MISCREG_WATCHHI3,
+ MISCREG_WATCHHI4,
+ MISCREG_WATCHHI5,
+ MISCREG_WATCHHI6,
+ MISCREG_WATCHHI7,
+
+ MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
+
+ //Bank 21: 168-175
+
+ //Bank 22: 176-183
+
+ MISCREG_DEBUG = 184, //Bank 23: 184-191
+ MISCREG_TRACE_CONTROL1,
+ MISCREG_TRACE_CONTROL2,
+ MISCREG_USER_TRACE_DATA,
+ MISCREG_TRACE_BPC,
+
+ MISCREG_DEPC = 192, //Bank 24: 192-199
+
+ MISCREG_PERFCNT0 = 200, //Bank 25: 200-207
+ MISCREG_PERFCNT1,
+ MISCREG_PERFCNT2,
+ MISCREG_PERFCNT3,
+ MISCREG_PERFCNT4,
+ MISCREG_PERFCNT5,
+ MISCREG_PERFCNT6,
+ MISCREG_PERFCNT7,
+
+ MISCREG_ERRCTL = 208, //Bank 26: 208-215
+
+ MISCREG_CACHEERR0 = 216, //Bank 27: 216-223
+ MISCREG_CACHEERR1,
+ MISCREG_CACHEERR2,
+ MISCREG_CACHEERR3,
+
+ MISCREG_TAGLO0 = 224, //Bank 28: 224-231
+ MISCREG_DATALO1,
+ MISCREG_TAGLO2,
+ MISCREG_DATALO3,
+ MISCREG_TAGLO4,
+ MISCREG_DATALO5,
+ MISCREG_TAGLO6,
+ MISCREG_DATALO7,
+
+ MISCREG_TAGHI0 = 232, //Bank 29: 232-239
+ MISCREG_DATAHI1,
+ MISCREG_TAGHI2,
+ MISCREG_DATAHI3,
+ MISCREG_TAGHI4,
+ MISCREG_DATAHI5,
+ MISCREG_TAGHI6,
+ MISCREG_DATAHI7,
+
+
+ MISCREG_ERROR_EPC = 240, //Bank 30: 240-247
+
+ MISCREG_DESAVE = 248, //Bank 31: 248-256
+
+ MISCREG_LLFLAG = 257,
+ MISCREG_TP_VALUE,
+
+ MISCREG_NUMREGS
+};
+
+} // namespace MipsISA
+
+#endif
diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc
index 9d71792..30efb36 100644
--- a/src/arch/mips/remote_gdb.cc
+++ b/src/arch/mips/remote_gdb.cc
@@ -136,6 +136,9 @@
#include <string>
#include "arch/mips/decoder.hh"
+#include "arch/mips/regs/float.hh"
+#include "arch/mips/regs/int.hh"
+#include "arch/mips/regs/misc.hh"
#include "blobs/gdb_xml_mips.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
diff --git a/src/arch/mips/remote_gdb.hh b/src/arch/mips/remote_gdb.hh
index 2119d8e..2084ec8 100644
--- a/src/arch/mips/remote_gdb.hh
+++ b/src/arch/mips/remote_gdb.hh
@@ -31,7 +31,6 @@
#ifndef __ARCH_MIPS_REMOTE_GDB_HH__
#define __ARCH_MIPS_REMOTE_GDB_HH__
-#include "arch/mips/registers.hh"
#include "base/bitfield.hh"
#include "base/remote_gdb.hh"
diff --git a/src/arch/mips/se_workload.hh b/src/arch/mips/se_workload.hh
index 55c605d..63eba3c 100644
--- a/src/arch/mips/se_workload.hh
+++ b/src/arch/mips/se_workload.hh
@@ -28,7 +28,7 @@
#ifndef __ARCH_MIPS_SE_WORKLOAD_HH__
#define __ARCH_MIPS_SE_WORKLOAD_HH__
-#include "arch/mips/registers.hh"
+#include "arch/mips/regs/int.hh"
#include "params/MipsSEWorkload.hh"
#include "sim/se_workload.hh"
#include "sim/syscall_abi.hh"
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index e892e71..fe41249 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -30,7 +30,9 @@
#include <cmath>
-#include "arch/mips/registers.hh"
+#include "arch/mips/regs/float.hh"
+#include "arch/mips/regs/int.hh"
+#include "arch/mips/regs/misc.hh"
#include "base/bitfield.hh"
#include "base/logging.hh"
#include "cpu/static_inst.hh"
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 4709692..8d35529 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -29,7 +29,9 @@
#ifndef __ARCH_MIPS_UTILITY_HH__
#define __ARCH_MIPS_UTILITY_HH__
+
#include "arch/mips/page_size.hh"
+#include "arch/mips/regs/misc.hh"
#include "arch/mips/types.hh"
#include "base/logging.hh"
#include "base/types.hh"
9 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41739
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia15c75547e74bf2f784fac5b3063159e0c79a00c
Gerrit-Change-Number: 41739
Gerrit-PatchSet: 11
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Boris Shingarov <shinga...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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