Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42968 )
Change subject: arch,cpu,sim: Move the null and nop StaticInstPtrs to their
own files.
......................................................................
arch,cpu,sim: Move the null and nop StaticInstPtrs to their own files.
The nullStaticInstPtr was low overhead, but the nopStaticInstPtr needed
an actual StaticInst implementation it could point to, and that brought
with it some (minor) additional dependencies. Specifically, the
implementation of advancePC needs the definition of TheISA::PCState,
while all other signatures/impementations in StaticInst are already
passing around that type by reference or could be made to, reducing
dependencies further.
Change-Id: I9ac6a6e5a3106858ea1fc727648f61dc39738a59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42968
Reviewed-by: Gabe Black <gabe.bl...@gmail.com>
Maintainer: Gabe Black <gabe.bl...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/faults.hh
M src/arch/generic/debugfaults.hh
M src/arch/mips/faults.hh
M src/arch/riscv/faults.hh
M src/arch/sparc/faults.hh
M src/arch/x86/faults.hh
M src/cpu/SConscript
M src/cpu/checker/cpu_impl.hh
M src/cpu/minor/dyn_inst.cc
M src/cpu/minor/fetch2.cc
A src/cpu/nop_static_inst.cc
A src/cpu/nop_static_inst.hh
A src/cpu/null_static_inst.cc
A src/cpu/null_static_inst.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/pred/tage_base.hh
M src/cpu/simple/base.cc
M src/cpu/static_inst.cc
M src/cpu/static_inst.hh
M src/sim/faults.hh
21 files changed, 245 insertions(+), 100 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 463af12..a477c75 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -46,6 +46,7 @@
#include "arch/arm/regs/misc.hh"
#include "arch/arm/types.hh"
#include "base/logging.hh"
+#include "cpu/null_static_inst.hh"
#include "sim/faults.hh"
#include "sim/full_system.hh"
@@ -221,9 +222,9 @@
MiscRegIndex getFaultAddrReg64() const;
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
void invoke64(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
+ nullStaticInstPtr);
void update(ThreadContext *tc);
bool isResetSPSR(){ return bStep; }
@@ -295,7 +296,7 @@
public:
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
};
class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
@@ -323,7 +324,7 @@
{}
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
bool routeToHyp(ThreadContext *tc) const override;
ExceptionClass ec(ThreadContext *tc) const override;
uint32_t iss() const override;
@@ -344,7 +345,7 @@
}
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
bool routeToHyp(ThreadContext *tc) const override;
ExceptionClass ec(ThreadContext *tc) const override;
uint32_t iss() const override;
@@ -361,7 +362,7 @@
}
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
ExceptionClass ec(ThreadContext *tc) const override;
uint32_t iss() const override;
uint32_t vectorCatchFlag() const override { return 0x00000400; }
@@ -467,7 +468,7 @@
bool getFaultVAddr(Addr &va) const override;
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
FSR getFsr(ThreadContext *tc) const override;
uint8_t getFaultStatusCode(ThreadContext *tc) const;
@@ -590,7 +591,7 @@
PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC)
{}
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
bool routeToHyp(ThreadContext *tc) const override;
};
@@ -608,7 +609,7 @@
public:
SystemError();
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
bool routeToMonitor(ThreadContext *tc) const override;
bool routeToHyp(ThreadContext *tc) const override;
};
@@ -629,7 +630,7 @@
Addr vAddr;
public:
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
HardwareBreakpoint(Addr _vaddr, uint32_t _iss);
bool routeToHyp(ThreadContext *tc) const override;
ExceptionClass ec(ThreadContext *tc) const override;
@@ -645,7 +646,7 @@
public:
Watchpoint(ExtMachInst _mach_inst, Addr _vaddr, bool _write, bool _cm);
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
bool routeToHyp(ThreadContext *tc) const override;
uint32_t iss() const override;
ExceptionClass ec(ThreadContext *tc) const override;
@@ -671,7 +672,7 @@
public:
ArmSev () {}
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
};
/// Illegal Instruction Set State fault (AArch64 only)
diff --git a/src/arch/generic/debugfaults.hh
b/src/arch/generic/debugfaults.hh
index 5c3982f..dd95f2c 100644
--- a/src/arch/generic/debugfaults.hh
+++ b/src/arch/generic/debugfaults.hh
@@ -41,6 +41,7 @@
#include <string>
#include "base/logging.hh"
+#include "cpu/null_static_inst.hh"
#include "cpu/thread_context.hh"
#include "sim/faults.hh"
@@ -74,7 +75,7 @@
void
invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override
+ nullStaticInstPtr) override
{
debugFunc();
advancePC(tc, inst);
@@ -106,7 +107,7 @@
void
invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override
+ nullStaticInstPtr) override
{
if (!once) {
once = true;
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 9875ab6..aeb37a7 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -32,6 +32,7 @@
#include "arch/mips/pra_constants.hh"
#include "arch/mips/regs/misc.hh"
+#include "cpu/null_static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
#include "sim/faults.hh"
@@ -99,7 +100,7 @@
}
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
+ nullStaticInstPtr);
};
template <typename T>
@@ -131,7 +132,7 @@
{
public:
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
+ nullStaticInstPtr);
};
@@ -139,14 +140,14 @@
{
public:
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
+ nullStaticInstPtr);
};
class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
{
public:
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
+ nullStaticInstPtr);
};
class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
@@ -159,7 +160,7 @@
void
invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr)
+ nullStaticInstPtr)
{
MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
if (FullSystem) {
@@ -194,7 +195,7 @@
void
invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr)
+ nullStaticInstPtr)
{
MipsFault<T>::invoke(tc, inst);
if (FullSystem)
@@ -247,7 +248,7 @@
void
invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr)
+ nullStaticInstPtr)
{
if (FullSystem) {
DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name());
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index 4516e35..b26ae73 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -35,6 +35,7 @@
#include "arch/riscv/isa.hh"
#include "arch/riscv/registers.hh"
+#include "cpu/null_static_inst.hh"
#include "cpu/thread_context.hh"
#include "sim/faults.hh"
@@ -121,7 +122,7 @@
FaultName name() const override { return _name; }
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
};
class InterruptFault : public RiscvFault
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index 38f9033..814475f 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -29,6 +29,7 @@
#ifndef __SPARC_FAULTS_HH__
#define __SPARC_FAULTS_HH__
+#include "cpu/null_static_inst.hh"
#include "cpu/static_inst.hh"
#include "sim/faults.hh"
@@ -69,7 +70,7 @@
{}
};
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
+ nullStaticInstPtr);
virtual TrapType trapType() = 0;
virtual FaultPriority priority() = 0;
virtual FaultStat & countStat() = 0;
@@ -98,7 +99,7 @@
{
public:
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
+ nullStaticInstPtr);
};
class WatchDogReset : public SparcFault<WatchDogReset> {};
@@ -212,7 +213,7 @@
FastInstructionAccessMMUMiss() : vaddr(0)
{}
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
+ nullStaticInstPtr);
};
class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss>
@@ -225,7 +226,7 @@
FastDataAccessMMUMiss() : vaddr(0)
{}
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
+ nullStaticInstPtr);
};
class FastDataAccessProtection : public
SparcFault<FastDataAccessProtection> {};
@@ -244,7 +245,7 @@
SpillNNormal(uint32_t n) : EnumeratedFault<SpillNNormal>(n) {;}
// These need to be handled specially to enable spill traps in SE
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
+ nullStaticInstPtr);
};
class SpillNOther : public EnumeratedFault<SpillNOther>
@@ -261,7 +262,7 @@
{}
// These need to be handled specially to enable fill traps in SE
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
+ nullStaticInstPtr);
};
class FillNOther : public EnumeratedFault<FillNOther>
@@ -278,7 +279,7 @@
{}
// In SE, trap instructions are requesting services from the OS.
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
+ nullStaticInstPtr);
};
/*
diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh
index 7dfd36c..9b6d488 100644
--- a/src/arch/x86/faults.hh
+++ b/src/arch/x86/faults.hh
@@ -43,6 +43,7 @@
#include "arch/x86/tlb.hh"
#include "base/bitunion.hh"
#include "base/logging.hh"
+#include "cpu/null_static_inst.hh"
#include "sim/faults.hh"
namespace X86ISA
@@ -69,7 +70,7 @@
virtual bool isSoft() { return false; }
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
virtual std::string describe() const;
@@ -98,7 +99,7 @@
using X86FaultBase::X86FaultBase;
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
};
// Base class for x86 aborts which seem to be catastrophic failures.
@@ -108,7 +109,7 @@
using X86FaultBase::X86FaultBase;
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
};
// Base class for x86 interrupts.
@@ -129,7 +130,7 @@
void
invoke(ThreadContext *tc, const StaticInstPtr &inst=
- StaticInst::nullStaticInstPtr) override
+ nullStaticInstPtr) override
{
panic("Unimplemented instruction!");
}
@@ -211,7 +212,7 @@
InvalidOpcode() : X86Fault("Invalid-Opcode", "#UD", 6) {}
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
};
class DeviceNotAvailable : public X86Fault
@@ -290,7 +291,7 @@
void
invoke(ThreadContext *tc, const StaticInstPtr &inst=
- StaticInst::nullStaticInstPtr);
+ nullStaticInstPtr);
virtual std::string describe() const;
};
@@ -351,7 +352,7 @@
{}
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
};
class StartupInterrupt : public X86Interrupt
@@ -362,7 +363,7 @@
{}
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
};
class SoftwareInterrupt : public X86Interrupt
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 41af2bf..83a78e2 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -102,6 +102,8 @@
Source('func_unit.cc')
Source('inteltrace.cc')
Source('nativetrace.cc')
+Source('nop_static_inst.cc')
+Source('null_static_inst.cc')
Source('profile.cc')
Source('reg_class.cc')
Source('static_inst.cc')
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 64a1767..7f1a2d7 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -48,6 +48,7 @@
#include "base/refcnt.hh"
#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
+#include "cpu/null_static_inst.hh"
#include "cpu/reg_class.hh"
#include "cpu/simple_thread.hh"
#include "cpu/static_inst.hh"
@@ -63,13 +64,13 @@
Checker<Impl>::advancePC(const Fault &fault)
{
if (fault != NoFault) {
- curMacroStaticInst = StaticInst::nullStaticInstPtr;
+ curMacroStaticInst = nullStaticInstPtr;
fault->invoke(tc, curStaticInst);
thread->decoder.reset();
} else {
if (curStaticInst) {
if (curStaticInst->isLastMicroop())
- curMacroStaticInst = StaticInst::nullStaticInstPtr;
+ curMacroStaticInst = nullStaticInstPtr;
TheISA::PCState pcState = thread->pcState();
curStaticInst->advancePC(pcState);
thread->pcState(pcState);
@@ -110,7 +111,7 @@
}
boundaryInst = NULL;
thread->decoder.reset();
- curMacroStaticInst = StaticInst::nullStaticInstPtr;
+ curMacroStaticInst = nullStaticInstPtr;
}
template <class Impl>
@@ -384,7 +385,7 @@
willChangePC = true;
newPCState = thread->pcState();
DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
- curMacroStaticInst = StaticInst::nullStaticInstPtr;
+ curMacroStaticInst = nullStaticInstPtr;
}
} else {
advancePC(fault);
diff --git a/src/cpu/minor/dyn_inst.cc b/src/cpu/minor/dyn_inst.cc
index 8723488..1e34a88 100644
--- a/src/cpu/minor/dyn_inst.cc
+++ b/src/cpu/minor/dyn_inst.cc
@@ -44,6 +44,7 @@
#include "arch/registers.hh"
#include "cpu/base.hh"
#include "cpu/minor/trace.hh"
+#include "cpu/null_static_inst.hh"
#include "cpu/reg_class.hh"
#include "debug/MinorExecute.hh"
#include "enums/OpClass.hh"
@@ -79,7 +80,7 @@
MinorDynInst::init()
{
if (!bubbleInst) {
- bubbleInst = new MinorDynInst(StaticInst::nullStaticInstPtr);
+ bubbleInst = new MinorDynInst(nullStaticInstPtr);
assert(bubbleInst->isBubble());
/* Make bubbleInst immortal */
bubbleInst->incref();
diff --git a/src/cpu/minor/fetch2.cc b/src/cpu/minor/fetch2.cc
index 5974bd8..1342e67 100644
--- a/src/cpu/minor/fetch2.cc
+++ b/src/cpu/minor/fetch2.cc
@@ -43,6 +43,7 @@
#include "base/logging.hh"
#include "base/trace.hh"
#include "cpu/minor/pipeline.hh"
+#include "cpu/null_static_inst.hh"
#include "cpu/pred/bpred_unit.hh"
#include "debug/Branch.hh"
#include "debug/Fetch.hh"
@@ -355,8 +356,7 @@
/* Make a new instruction and pick up the line, stream,
* prediction, thread ids from the incoming line */
- dyn_inst = new MinorDynInst(
- StaticInst::nullStaticInstPtr, line_in->id);
+ dyn_inst = new MinorDynInst(nullStaticInstPtr,
line_in->id);
/* Fetch and prediction sequence numbers originate here */
dyn_inst->id.fetchSeqNum = fetch_info.fetchSeqNum;
diff --git a/src/cpu/nop_static_inst.cc b/src/cpu/nop_static_inst.cc
new file mode 100644
index 0000000..bc40227
--- /dev/null
+++ b/src/cpu/nop_static_inst.cc
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cpu/nop_static_inst.hh"
+
+#include "cpu/static_inst.hh"
+
+namespace
+{
+
+class NopStaticInst : public StaticInst
+{
+ public:
+ NopStaticInst() : StaticInst("gem5 nop", No_OpClass) {}
+
+ Fault
+ execute(ExecContext *xc, Trace::InstRecord *traceData) const override
+ {
+ return NoFault;
+ }
+
+ void
+ advancePC(TheISA::PCState &pcState) const override
+ {
+ pcState.advance();
+ }
+
+ std::string
+ generateDisassembly(Addr pc,
+ const Loader::SymbolTable *symtab) const override
+ {
+ return mnemonic;
+ }
+};
+
+}
+
+StaticInstPtr nopStaticInstPtr = new NopStaticInst;
diff --git a/src/cpu/nop_static_inst.hh b/src/cpu/nop_static_inst.hh
new file mode 100644
index 0000000..9397f85
--- /dev/null
+++ b/src/cpu/nop_static_inst.hh
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2021 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_NOP_STATIC_INST_HH__
+#define __CPU_NOP_STATIC_INST_HH__
+
+#include "cpu/static_inst_fwd.hh"
+
+/// Pointer to a statically allocated generic "nop" instruction object.
+extern StaticInstPtr nopStaticInstPtr;
+
+#endif // __CPU_NOP_STATIC_INST_HH__
diff --git a/src/cpu/null_static_inst.cc b/src/cpu/null_static_inst.cc
new file mode 100644
index 0000000..b9011c7
--- /dev/null
+++ b/src/cpu/null_static_inst.cc
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cpu/null_static_inst.hh"
+
+#include "cpu/static_inst.hh"
+
+const StaticInstPtr nullStaticInstPtr;
diff --git a/src/cpu/null_static_inst.hh b/src/cpu/null_static_inst.hh
new file mode 100644
index 0000000..361c566
--- /dev/null
+++ b/src/cpu/null_static_inst.hh
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2021 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_NULL_STATIC_INST_HH__
+#define __CPU_NULL_STATIC_INST_HH__
+
+#include "cpu/static_inst_fwd.hh"
+
+/// Statically allocated null StaticInstPtr.
+extern const StaticInstPtr nullStaticInstPtr;
+
+#endif // __CPU_NULL_STATIC_INST_HH__
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 896f71f..0531a5f 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -48,11 +48,12 @@
#include "base/loader/symtab.hh"
#include "base/logging.hh"
#include "config/the_isa.hh"
+#include "cpu/base.hh"
#include "cpu/checker/cpu.hh"
+#include "cpu/exetrace.hh"
+#include "cpu/null_static_inst.hh"
#include "cpu/o3/commit.hh"
#include "cpu/o3/thread_state.hh"
-#include "cpu/base.hh"
-#include "cpu/exetrace.hh"
#include "cpu/timebuf.hh"
#include "debug/Activity.hh"
#include "debug/Commit.hh"
@@ -1296,8 +1297,7 @@
// prevents external agents from changing any specific state
// that the trap need.
cpu->trap(inst_fault, tid,
- head_inst->notAnInst() ?
- StaticInst::nullStaticInstPtr :
+ head_inst->notAnInst() ? nullStaticInstPtr :
head_inst->staticInst);
// Exit state update mode to avoid accidental updating.
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 13e8643..43e3fa6 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -53,9 +53,11 @@
#include "base/types.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
+#include "cpu/exetrace.hh"
+#include "cpu/nop_static_inst.hh"
#include "cpu/o3/cpu.hh"
#include "cpu/o3/fetch.hh"
-#include "cpu/exetrace.hh"
+#include "cpu/o3/isa_specific.hh"
#include "debug/Activity.hh"
#include "debug/Drain.hh"
#include "debug/Fetch.hh"
@@ -68,7 +70,6 @@
#include "sim/eventq.hh"
#include "sim/full_system.hh"
#include "sim/system.hh"
-#include "cpu/o3/isa_specific.hh"
template<class Impl>
DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, const DerivO3CPUParams
¶ms)
@@ -698,8 +699,8 @@
DPRINTF(Fetch, "[tid:%i] Translation faulted, building noop.\n",
tid);
// We will use a nop in ordier to carry the fault.
- DynInstPtr instruction = buildInst(tid,
StaticInst::nopStaticInstPtr,
- NULL, fetchPC, fetchPC, false);
+ DynInstPtr instruction = buildInst(tid, nopStaticInstPtr, nullptr,
+ fetchPC, fetchPC, false);
instruction->setNotAnInst();
instruction->setPredTarg(fetchPC);
diff --git a/src/cpu/pred/tage_base.hh b/src/cpu/pred/tage_base.hh
index dce9619..4199299 100644
--- a/src/cpu/pred/tage_base.hh
+++ b/src/cpu/pred/tage_base.hh
@@ -51,6 +51,7 @@
#include <vector>
#include "base/statistics.hh"
+#include "cpu/null_static_inst.hh"
#include "cpu/static_inst.hh"
#include "params/TAGEBase.hh"
#include "sim/sim_object.hh"
@@ -287,7 +288,7 @@
virtual void updateHistories(
ThreadID tid, Addr branch_pc, bool taken, BranchInfo* b,
bool speculative,
- const StaticInstPtr & inst = StaticInst::nullStaticInstPtr,
+ const StaticInstPtr & inst = nullStaticInstPtr,
Addr target = MaxAddr);
/**
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index fe3e34d..b2d66f7 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -53,6 +53,7 @@
#include "cpu/checker/cpu.hh"
#include "cpu/checker/thread_context.hh"
#include "cpu/exetrace.hh"
+#include "cpu/null_static_inst.hh"
#include "cpu/pred/bpred_unit.hh"
#include "cpu/simple/exec_context.hh"
#include "cpu/simple_thread.hh"
@@ -472,13 +473,13 @@
//Since we're moving to a new pc, zero out the offset
t_info.fetchOffset = 0;
if (fault != NoFault) {
- curMacroStaticInst = StaticInst::nullStaticInstPtr;
+ curMacroStaticInst = nullStaticInstPtr;
fault->invoke(threadContexts[curThread], curStaticInst);
thread->decoder.reset();
} else {
if (curStaticInst) {
if (curStaticInst->isLastMicroop())
- curMacroStaticInst = StaticInst::nullStaticInstPtr;
+ curMacroStaticInst = nullStaticInstPtr;
TheISA::PCState pcState = thread->pcState();
curStaticInst->advancePC(pcState);
thread->pcState(pcState);
diff --git a/src/cpu/static_inst.cc b/src/cpu/static_inst.cc
index c42b1d2..c389f21 100644
--- a/src/cpu/static_inst.cc
+++ b/src/cpu/static_inst.cc
@@ -30,40 +30,6 @@
#include <iostream>
-#include "sim/core.hh"
-
-namespace {
-
-class NopStaticInst : public StaticInst
-{
- public:
- NopStaticInst() : StaticInst("gem5 nop", No_OpClass) {}
-
- Fault
- execute(ExecContext *xc, Trace::InstRecord *traceData) const override
- {
- return NoFault;
- }
-
- void
- advancePC(TheISA::PCState &pcState) const override
- {
- pcState.advance();
- }
-
- std::string
- generateDisassembly(Addr pc,
- const Loader::SymbolTable *symtab) const override
- {
- return mnemonic;
- }
-};
-
-}
-
-StaticInstPtr StaticInst::nullStaticInstPtr;
-StaticInstPtr StaticInst::nopStaticInstPtr = new NopStaticInst;
-
bool
StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
TheISA::PCState &tgt) const
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 20411e7..78efd6d 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -251,9 +251,6 @@
/// Pointer to a statically allocated "null" instruction object.
static StaticInstPtr nullStaticInstPtr;
- /// Pointer to a statically allocated generic "nop" instruction object.
- static StaticInstPtr nopStaticInstPtr;
-
virtual uint64_t getEMI() const { return 0; }
protected:
diff --git a/src/sim/faults.hh b/src/sim/faults.hh
index 2a96ce9..aaa689e 100644
--- a/src/sim/faults.hh
+++ b/src/sim/faults.hh
@@ -42,6 +42,7 @@
#define __FAULTS_HH__
#include "base/types.hh"
+#include "cpu/null_static_inst.hh"
#include "cpu/static_inst.hh"
#include "mem/htm.hh"
#include "sim/stats.hh"
@@ -56,7 +57,7 @@
public:
virtual FaultName name() const = 0;
virtual void invoke(ThreadContext * tc, const StaticInstPtr &inst=
- StaticInst::nullStaticInstPtr);
+ nullStaticInstPtr);
virtual ~FaultBase() {};
};
@@ -73,7 +74,7 @@
return "Unimplemented simulator feature";
}
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
};
// A fault to trigger a system call in SE mode.
@@ -82,7 +83,7 @@
const char *name() const override { return "syscall_fault"; }
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
};
class ReExec : public FaultBase
@@ -90,7 +91,7 @@
public:
virtual FaultName name() const override { return "Re-execution fault";
}
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
};
/*
@@ -106,7 +107,7 @@
FaultName name() const override { return "System call retry fault"; }
SyscallRetryFault() {}
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
};
class GenericPageTableFault : public FaultBase
@@ -117,7 +118,7 @@
FaultName name() const override { return "Generic page table fault"; }
GenericPageTableFault(Addr va) : vaddr(va) {}
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
Addr getFaultVAddr() const { return vaddr; }
};
@@ -129,7 +130,7 @@
FaultName name() const override { return "Generic alignment fault"; }
GenericAlignmentFault(Addr va) : vaddr(va) {}
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
Addr getFaultVAddr() const { return vaddr; }
};
@@ -149,7 +150,7 @@
uint64_t getHtmUid() const { return htmUid; }
HtmFailureFaultCause getHtmFailureFaultCause() const { return cause; }
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
+ nullStaticInstPtr) override;
};
#endif // __FAULTS_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9ac6a6e5a3106858ea1fc727648f61dc39738a59
Gerrit-Change-Number: 42968
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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