Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42386 )
Change subject: arch,mem: Use szext instead of sext as appropriate.
......................................................................
arch,mem: Use szext instead of sext as appropriate.
When the value being passed to sext needs to be masked first, szext can
be used instead without the masking.
Change-Id: I98c99ad2731216fe8ccf1253f5ac3891fe03b1de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42386
Reviewed-by: Daniel Carvalho <oda...@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbr...@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbr...@ucdavis.edu>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/amdgpu/gcn3/insts/instructions.cc
M src/arch/arm/insts/vfp.cc
M src/arch/mips/isa/decoder.isa
M src/arch/sparc/insts/blockmem.hh
M src/arch/sparc/insts/branch.hh
M src/arch/sparc/insts/integer.hh
M src/arch/sparc/insts/mem.hh
M src/arch/sparc/isa/decoder.isa
M src/arch/sparc/tlb.cc
M src/mem/cache/compressors/dictionary_compressor.hh
M src/mem/cache/compressors/fpc.hh
11 files changed, 31 insertions(+), 41 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/gcn3/insts/instructions.cc
b/src/arch/amdgpu/gcn3/insts/instructions.cc
index ad04a4a..8cadff7 100644
--- a/src/arch/amdgpu/gcn3/insts/instructions.cc
+++ b/src/arch/amdgpu/gcn3/insts/instructions.cc
@@ -5728,8 +5728,7 @@
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (wf->execMask(lane)) {
- vdst[lane] = sext<24>(bits(src0[lane], 23, 0))
- * sext<24>(bits(src1[lane], 23, 0));
+ vdst[lane] = szext<24>(src0[lane]) * szext<24>(src1[lane]);
}
}
@@ -5760,10 +5759,8 @@
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (wf->execMask(lane)) {
- VecElemI64 tmp_src0
- = (VecElemI64)sext<24>(bits(src0[lane], 23, 0));
- VecElemI64 tmp_src1
- = (VecElemI64)sext<24>(bits(src1[lane], 23, 0));
+ VecElemI64 tmp_src0 = (VecElemI64)szext<24>(src0[lane]);
+ VecElemI64 tmp_src1 = (VecElemI64)szext<24>(src1[lane]);
vdst[lane] = (VecElemI32)((tmp_src0 * tmp_src1) >> 32);
}
@@ -23563,8 +23560,7 @@
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (wf->execMask(lane)) {
- vdst[lane] = sext<24>(bits(src0[lane], 23, 0))
- * sext<24>(bits(src1[lane], 23, 0));
+ vdst[lane] = szext<24>(src0[lane]) * szext<24>(src1[lane]);
}
}
@@ -23605,10 +23601,8 @@
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (wf->execMask(lane)) {
- VecElemI64 tmp_src0
- = (VecElemI64)sext<24>(bits(src0[lane], 23, 0));
- VecElemI64 tmp_src1
- = (VecElemI64)sext<24>(bits(src1[lane], 23, 0));
+ VecElemI64 tmp_src0 = (VecElemI64)szext<24>(src0[lane]);
+ VecElemI64 tmp_src1 = (VecElemI64)szext<24>(src1[lane]);
vdst[lane] = (VecElemI32)((tmp_src0 * tmp_src1) >> 32);
}
@@ -27785,8 +27779,8 @@
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (wf->execMask(lane)) {
- vdst[lane] = sext<24>(bits(src0[lane], 23, 0))
- * sext<24>(bits(src1[lane], 23, 0)) + src2[lane];
+ vdst[lane] = szext<24>(src0[lane])
+ * szext<24>(src1[lane]) + src2[lane];
}
}
diff --git a/src/arch/arm/insts/vfp.cc b/src/arch/arm/insts/vfp.cc
index c39b94a..4729039 100644
--- a/src/arch/arm/insts/vfp.cc
+++ b/src/arch/arm/insts/vfp.cc
@@ -692,9 +692,9 @@
{
fesetround(FeRoundNearest);
if (width == 16)
- val = sext<16>(val & mask(16));
+ val = szext<16>(val);
else if (width == 32)
- val = sext<32>(val & mask(32));
+ val = szext<32>(val);
else if (width != 64)
panic("Unsupported width %d", width);
@@ -731,9 +731,9 @@
{
fesetround(FeRoundNearest);
if (width == 16)
- val = sext<16>(val & mask(16));
+ val = szext<16>(val);
else if (width == 32)
- val = sext<32>(val & mask(32));
+ val = szext<32>(val);
else if (width != 64)
panic("Unsupported width %d", width);
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index ea2b43a..2e56a04 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -2445,12 +2445,11 @@
}
}});
0x3: shilov({{
- if ((int64_t)sext<6>(Rs_sw<5:0>) <
0) {
+ if ((int64_t)szext<6>(Rs_sw) < 0) {
dspac = (uint64_t)dspac <<
- -sext<6>(Rs_sw<5:0>);
+ -sext<6>(Rs_sw);
} else {
- dspac = (uint64_t)dspac >>
- sext<6>(Rs_sw<5:0>);
+ dspac = (uint64_t)dspac >>
szext<6>(Rs_sw);
}
}});
0x7: mthlip({{
diff --git a/src/arch/sparc/insts/blockmem.hh
b/src/arch/sparc/insts/blockmem.hh
index 0528b6a..f5bc397 100644
--- a/src/arch/sparc/insts/blockmem.hh
+++ b/src/arch/sparc/insts/blockmem.hh
@@ -75,7 +75,7 @@
BlockMemImmMicro(const char *mnem, ExtMachInst _machInst,
OpClass __opClass, int8_t _offset) :
BlockMemMicro(mnem, _machInst, __opClass, _offset),
- imm(sext<13>(bits(_machInst, 12, 0)))
+ imm(szext<13>(_machInst))
{}
std::string generateDisassembly(
diff --git a/src/arch/sparc/insts/branch.hh b/src/arch/sparc/insts/branch.hh
index 03842bf..915c0d8 100644
--- a/src/arch/sparc/insts/branch.hh
+++ b/src/arch/sparc/insts/branch.hh
@@ -77,8 +77,7 @@
protected:
// Constructor
BranchNBits(const char *mnem, ExtMachInst _machInst, OpClass
__opClass) :
- BranchDisp(mnem, _machInst, __opClass,
- sext<bits + 2>((_machInst & mask(bits)) << 2))
+ BranchDisp(mnem, _machInst, __opClass, szext<bits>(_machInst) << 2)
{}
};
@@ -105,8 +104,7 @@
protected:
// Constructor
BranchImm13(const char *mnem, ExtMachInst _machInst, OpClass
__opClass) :
- Branch(mnem, _machInst, __opClass),
- imm(sext<13>(bits(_machInst, 12, 0)))
+ Branch(mnem, _machInst, __opClass), imm(szext<13>(_machInst))
{}
std::string generateDisassembly(
diff --git a/src/arch/sparc/insts/integer.hh
b/src/arch/sparc/insts/integer.hh
index a38bebe..890ed05 100644
--- a/src/arch/sparc/insts/integer.hh
+++ b/src/arch/sparc/insts/integer.hh
@@ -83,7 +83,7 @@
protected:
// Constructor
IntOpImm10(const char *mnem, ExtMachInst _machInst, OpClass
__opClass) :
- IntOpImm(mnem, _machInst, __opClass, sext<10>(bits(_machInst, 9,
0)))
+ IntOpImm(mnem, _machInst, __opClass, szext<10>(_machInst))
{}
};
@@ -94,7 +94,7 @@
{
protected:
IntOpImm11(const char *mnem, ExtMachInst _machInst, OpClass
__opClass) :
- IntOpImm(mnem, _machInst, __opClass, sext<11>(bits(_machInst, 10,
0)))
+ IntOpImm(mnem, _machInst, __opClass, szext<11>(_machInst))
{}
};
@@ -105,7 +105,7 @@
{
protected:
IntOpImm13(const char *mnem, ExtMachInst _machInst, OpClass
__opClass) :
- IntOpImm(mnem, _machInst, __opClass, sext<13>(bits(_machInst, 12,
0)))
+ IntOpImm(mnem, _machInst, __opClass, szext<13>(_machInst))
{}
};
diff --git a/src/arch/sparc/insts/mem.hh b/src/arch/sparc/insts/mem.hh
index 929fa94..fb1f0ec 100644
--- a/src/arch/sparc/insts/mem.hh
+++ b/src/arch/sparc/insts/mem.hh
@@ -60,7 +60,7 @@
// Constructor
MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- Mem(mnem, _machInst, __opClass), imm(sext<13>(bits(_machInst, 12,
0)))
+ Mem(mnem, _machInst, __opClass), imm(szext<13>(_machInst))
{}
std::string generateDisassembly(
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index fb1d889..8535242 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -155,7 +155,7 @@
Y = Rd<63:32>;
}});
0x0B: smul({{
- Rd_sdw = sext<32>(Rs1_sdw<31:0>) *
sext<32>(Rs2_or_imm13<31:0>);
+ Rd_sdw = szext<32>(Rs1_sdw) * szext<32>(Rs2_or_imm13);
Y = Rd_sdw<63:32>;
}});
0x0C: subc({{Rd_sdw = Rs1_sdw + (~Rs2_or_imm13) + 1 -
Ccr<0:0>}});
@@ -215,8 +215,7 @@
Y = resTemp<63:32>;}});
0x1B: IntOpCcRes::smulcc({{
int64_t resTemp;
- Rd = resTemp = sext<32>(Rs1_sdw<31:0>) *
- sext<32>(Rs2_or_imm13<31:0>);
+ Rd = resTemp = szext<32>(Rs1_sdw) *
szext<32>(Rs2_or_imm13);
Y = resTemp<63:32>;}});
0x1C: subccc({{
int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 167ff03..1f587c0 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -1238,7 +1238,7 @@
itb->sfsr = data;
break;
case 0x30:
- itb->tag_access = sext<60>(bits(data, 59,0));
+ itb->tag_access = szext<60>(data);
break;
default:
goto doMmuWriteError;
@@ -1314,7 +1314,7 @@
sfsr = data;
break;
case 0x30:
- tag_access = sext<60>(bits(data, 59,0));
+ tag_access = szext<60>(data);
break;
case 0x80:
tc->setMiscReg(MISCREG_MMU_PART_ID, data);
diff --git a/src/mem/cache/compressors/dictionary_compressor.hh
b/src/mem/cache/compressors/dictionary_compressor.hh
index fe70b59..ead3656 100644
--- a/src/mem/cache/compressors/dictionary_compressor.hh
+++ b/src/mem/cache/compressors/dictionary_compressor.hh
@@ -776,7 +776,7 @@
const DictionaryEntry& dict_bytes, const int match_location)
{
const T data = DictionaryCompressor<T>::fromDictionaryEntry(bytes);
- return data == sext<N>(data & mask(N));
+ return data == (T)szext<N>(data);
}
DictionaryEntry
diff --git a/src/mem/cache/compressors/fpc.hh
b/src/mem/cache/compressors/fpc.hh
index 820979f..dc54acd 100644
--- a/src/mem/cache/compressors/fpc.hh
+++ b/src/mem/cache/compressors/fpc.hh
@@ -266,16 +266,16 @@
int16_t(data & mask(16)),
int16_t((data >> 16) & mask(16))
};
- return (halfwords[0] == sext<8>(halfwords[0] & mask(8))) &&
- (halfwords[1] == sext<8>(halfwords[1] & mask(8)));
+ return (halfwords[0] == (uint16_t)szext<8>(halfwords[0])) &&
+ (halfwords[1] == (uint16_t)szext<8>(halfwords[1]));
}
DictionaryEntry
decompress(const DictionaryEntry dict_bytes) const override
{
uint16_t halfwords[2] = {
- uint16_t(sext<8>(extendedBytes[0]) & mask(16)),
- uint16_t(sext<8>(extendedBytes[1]) & mask(16))
+ (uint16_t)szext<8>(extendedBytes[0]),
+ (uint16_t)szext<8>(extendedBytes[1])
};
return toDictionaryEntry((halfwords[1] << 16) | halfwords[0]);
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I98c99ad2731216fe8ccf1253f5ac3891fe03b1de
Gerrit-Change-Number: 42386
Gerrit-PatchSet: 6
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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