Gabriel Busnot has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45028 )
Change subject: misc: Replace assert with gem5_assert
......................................................................
misc: Replace assert with gem5_assert
Replacement performed with a basic sed plus some filtering not affect the
use of
the verb assert in comments. cassert is no longer included when gem5_assert
only
is used.
Change-Id: Ide2718de8c987f6ab2bed084efc68f8aa75f17de
---
M src/arch/amdgpu/gcn3/gpu_mem_helpers.hh
M src/arch/amdgpu/gcn3/insts/inst_util.hh
M src/arch/amdgpu/gcn3/insts/instructions.cc
M src/arch/amdgpu/gcn3/insts/instructions.hh
M src/arch/amdgpu/gcn3/insts/op_encodings.cc
M src/arch/amdgpu/gcn3/operand.hh
M src/arch/amdgpu/vega/gpu_mem_helpers.hh
M src/arch/amdgpu/vega/insts/inst_util.hh
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
M src/arch/amdgpu/vega/insts/op_encodings.cc
M src/arch/amdgpu/vega/operand.hh
M src/arch/arm/decoder.cc
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/iris/thread_context.cc
M src/arch/arm/fastmodel/iris/tlb.cc
M src/arch/arm/faults.cc
M src/arch/arm/htm.cc
M src/arch/arm/insts/fplib.cc
M src/arch/arm/insts/macromem.cc
M src/arch/arm/insts/mem.hh
M src/arch/arm/insts/mem64.hh
M src/arch/arm/insts/misc64.hh
M src/arch/arm/insts/neon64_mem.hh
M src/arch/arm/insts/pred_inst.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/sve.cc
M src/arch/arm/insts/sve_macromem.hh
M src/arch/arm/insts/tme64ruby.cc
M src/arch/arm/insts/vfp.cc
M src/arch/arm/interrupts.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa_device.cc
M src/arch/arm/kvm/arm_cpu.cc
M src/arch/arm/kvm/gic.cc
M src/arch/arm/linux/fs_workload.cc
M src/arch/arm/linux/se_workload.cc
M src/arch/arm/locked_mem.hh
M src/arch/arm/mmu.hh
M src/arch/arm/nativetrace.cc
M src/arch/arm/pauth_helpers.cc
M src/arch/arm/pmu.cc
M src/arch/arm/pmu.hh
M src/arch/arm/regs/int.hh
M src/arch/arm/regs/misc.cc
M src/arch/arm/semihosting.cc
M src/arch/arm/stage2_lookup.cc
M src/arch/arm/stage2_mmu.cc
M src/arch/arm/system.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/tracers/tarmac_parser.hh
M src/arch/arm/utility.cc
M src/arch/generic/memhelpers.hh
M src/arch/generic/vec_pred_reg.hh
M src/arch/mips/interrupts.cc
M src/arch/mips/tlb.cc
M src/arch/power/interrupts.hh
M src/arch/power/tlb.cc
M src/arch/riscv/decoder.cc
M src/arch/riscv/interrupts.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/pagetable_walker.cc
M src/arch/riscv/tlb.cc
M src/arch/sparc/faults.cc
M src/arch/sparc/insts/micro.hh
M src/arch/sparc/interrupts.hh
M src/arch/sparc/isa.cc
M src/arch/sparc/isa.hh
M src/arch/sparc/nativetrace.cc
M src/arch/sparc/pagetable.hh
M src/arch/sparc/process.cc
M src/arch/sparc/tlb.cc
M src/arch/sparc/ua2005.cc
M src/arch/x86/bios/acpi.cc
M src/arch/x86/bios/e820.cc
M src/arch/x86/bios/smbios.cc
M src/arch/x86/cpuid.cc
M src/arch/x86/decoder.cc
M src/arch/x86/decoder.hh
M src/arch/x86/emulenv.cc
M src/arch/x86/faults.cc
M src/arch/x86/fs_workload.cc
M src/arch/x86/insts/macroop.hh
M src/arch/x86/insts/microldstop.hh
M src/arch/x86/insts/static_inst.cc
M src/arch/x86/interrupts.cc
M src/arch/x86/isa.cc
M src/arch/x86/linux/syscalls.cc
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/process.cc
M src/arch/x86/regs/misc.hh
M src/arch/x86/tlb.cc
M src/arch/x86/x86_traits.hh
M src/base/SConscript
M src/base/bitfield.hh
M src/base/cast.hh
M src/base/chunk_generator.hh
M src/base/circular_queue.hh
M src/base/debug.test.cc
M src/base/filters/base.hh
M src/base/filters/block_bloom_filter.cc
M src/base/filters/bulk_bloom_filter.cc
M src/base/filters/multi_bloom_filter.cc
M src/base/framebuffer.hh
M src/base/gtest/logging_mock.cc
M src/base/inet.cc
M src/base/intmath.hh
M src/base/loader/elf_object.cc
M src/base/loader/image_file_data.cc
M src/base/pixel.cc
M src/base/sat_counter.hh
M src/base/sat_counter.test.cc
M src/base/socket.test.cc
M src/base/statistics.cc
M src/base/statistics.hh
M src/base/stats/hdf5.cc
M src/base/stats/storage.cc
M src/base/stats/storage.hh
M src/base/stats/storage.test.cc
M src/base/stats/text.cc
M src/base/trie.hh
M src/base/types.hh
M src/base/vnc/vncinput.cc
M src/base/vnc/vncserver.cc
M src/cpu/activity.cc
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/inst_res.hh
M src/cpu/kvm/base.cc
M src/cpu/kvm/device.cc
M src/cpu/kvm/perfevent.cc
M src/cpu/kvm/timer.cc
M src/cpu/kvm/vm.cc
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/buffers.hh
M src/cpu/minor/cpu.cc
M src/cpu/minor/decode.cc
M src/cpu/minor/dyn_inst.cc
M src/cpu/minor/dyn_inst.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/execute.cc
M src/cpu/minor/fetch1.cc
M src/cpu/minor/fetch2.cc
M src/cpu/minor/lsq.cc
M src/cpu/minor/pipe_data.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/dep_graph.hh
M src/cpu/o3/dyn_inst.cc
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/free_list.hh
M src/cpu/o3/fu_pool.cc
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/o3/mem_dep_unit_impl.hh
M src/cpu/o3/probe/elastic_trace.cc
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/o3/rob_impl.hh
M src/cpu/o3/scoreboard.hh
M src/cpu/o3/store_set.cc
M src/cpu/pred/2bit_local.cc
M src/cpu/pred/2bit_local.hh
M src/cpu/pred/bi_mode.cc
M src/cpu/pred/bpred_unit.cc
M src/cpu/pred/btb.cc
M src/cpu/pred/loop_predictor.cc
M src/cpu/pred/loop_predictor.hh
M src/cpu/pred/ltage.cc
M src/cpu/pred/multiperspective_perceptron.cc
M src/cpu/pred/multiperspective_perceptron.hh
M src/cpu/pred/multiperspective_perceptron_tage.cc
M src/cpu/pred/simple_indirect.cc
M src/cpu/pred/statistical_corrector.cc
M src/cpu/pred/statistical_corrector.hh
M src/cpu/pred/tage.cc
M src/cpu/pred/tage_base.cc
M src/cpu/pred/tage_sc_l.cc
M src/cpu/pred/tournament.cc
M src/cpu/reg_class.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/base.cc
M src/cpu/simple/exec_context.hh
M src/cpu/simple/noncaching.cc
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/testers/directedtest/DirectedGenerator.cc
M src/cpu/testers/directedtest/InvalidateGenerator.cc
M src/cpu/testers/directedtest/RubyDirectedTester.cc
M src/cpu/testers/directedtest/SeriesRequestGenerator.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
M src/cpu/testers/gpu_ruby_test/address_manager.cc
M src/cpu/testers/gpu_ruby_test/cpu_thread.cc
M src/cpu/testers/gpu_ruby_test/dma_thread.cc
M src/cpu/testers/gpu_ruby_test/episode.cc
M src/cpu/testers/gpu_ruby_test/gpu_wavefront.cc
M src/cpu/testers/gpu_ruby_test/protocol_tester.cc
M src/cpu/testers/gpu_ruby_test/protocol_tester.hh
M src/cpu/testers/gpu_ruby_test/tester_thread.cc
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/rubytest/Check.cc
M src/cpu/testers/rubytest/CheckTable.cc
M src/cpu/testers/rubytest/RubyTester.cc
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/testers/traffic_gen/base.hh
M src/cpu/testers/traffic_gen/dram_gen.cc
M src/cpu/testers/traffic_gen/dram_rot_gen.cc
M src/cpu/testers/traffic_gen/hybrid_gen.cc
M src/cpu/testers/traffic_gen/linear_gen.cc
M src/cpu/testers/traffic_gen/nvm_gen.cc
M src/cpu/testers/traffic_gen/random_gen.cc
M src/cpu/testers/traffic_gen/strided_gen.cc
M src/cpu/testers/traffic_gen/trace_gen.cc
M src/cpu/testers/traffic_gen/traffic_gen.cc
M src/cpu/thread_context.cc
M src/cpu/thread_state.cc
M src/cpu/timebuf.hh
M src/cpu/trace/trace_cpu.cc
M src/cpu/trace/trace_cpu.hh
M src/cpu/translation.hh
M src/dev/arm/a9scu.cc
M src/dev/arm/amba_fake.cc
M src/dev/arm/css/mhu.cc
M src/dev/arm/energy_ctrl.cc
M src/dev/arm/flash_device.cc
M src/dev/arm/generic_timer.cc
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v2.hh
M src/dev/arm/gic_v2m.cc
M src/dev/arm/gic_v3.hh
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_its.cc
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/gpu_nomali.cc
M src/dev/arm/hdlcd.cc
M src/dev/arm/kmi.cc
M src/dev/arm/pl011.cc
M src/dev/arm/pl111.cc
M src/dev/arm/rtc_pl031.cc
M src/dev/arm/rv_ctrl.cc
M src/dev/arm/smmu_v3.cc
M src/dev/arm/smmu_v3_caches.cc
M src/dev/arm/smmu_v3_deviceifc.cc
M src/dev/arm/smmu_v3_proc.cc
M src/dev/arm/smmu_v3_transl.cc
M src/dev/arm/timer_cpulocal.cc
M src/dev/arm/timer_sp804.cc
M src/dev/arm/ufs_device.cc
M src/dev/arm/vgic.cc
M src/dev/arm/watchdog_sp805.cc
M src/dev/dma_device.cc
M src/dev/hsa/hsa_packet_processor.cc
M src/dev/hsa/hsa_packet_processor.hh
M src/dev/hsa/hw_scheduler.cc
M src/dev/i2c/bus.cc
M src/dev/intel_8254_timer.cc
M src/dev/intel_8254_timer.hh
M src/dev/io_device.cc
M src/dev/io_device.hh
M src/dev/isa_fake.cc
M src/dev/mc146818.cc
M src/dev/mips/malta_cchip.cc
M src/dev/net/dist_etherlink.cc
M src/dev/net/dist_etherlink.hh
M src/dev/net/dist_iface.cc
M src/dev/net/etherlink.cc
M src/dev/net/etherlink.hh
M src/dev/net/etherpkt.cc
M src/dev/net/etherswitch.cc
M src/dev/net/ethertap.cc
M src/dev/net/i8254xGBe.cc
M src/dev/net/i8254xGBe_defs.hh
M src/dev/net/ns_gige.cc
M src/dev/net/pktfifo.hh
M src/dev/net/sinic.cc
M src/dev/net/tcp_iface.cc
M src/dev/pci/copy_engine.cc
M src/dev/pci/copy_engine.hh
M src/dev/pci/device.hh
M src/dev/pci/host.cc
M src/dev/pixelpump.cc
M src/dev/ps2/device.cc
M src/dev/ps2/touchkit.cc
M src/dev/reg_bank.hh
M src/dev/riscv/clint.cc
M src/dev/riscv/plic.cc
M src/dev/serial/serial.cc
M src/dev/serial/simple.cc
M src/dev/serial/terminal.cc
M src/dev/sparc/dtod.cc
M src/dev/sparc/iob.cc
M src/dev/sparc/mm_disk.cc
M src/dev/storage/disk_image.cc
M src/dev/storage/ide_ctrl.cc
M src/dev/storage/ide_disk.cc
M src/dev/virtio/base.cc
M src/dev/virtio/base.hh
M src/dev/virtio/fs9p.cc
M src/dev/virtio/pci.cc
M src/dev/x86/cmos.cc
M src/dev/x86/i8042.cc
M src/dev/x86/i82094aa.cc
M src/dev/x86/i8254.cc
M src/dev/x86/i8259.cc
M src/dev/x86/intdev.hh
M src/dev/x86/pc.cc
M src/dev/x86/speaker.cc
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/dispatcher.cc
M src/gpu-compute/dyn_pool_manager.cc
M src/gpu-compute/exec_stage.cc
M src/gpu-compute/fetch_unit.cc
M src/gpu-compute/fetch_unit.hh
M src/gpu-compute/global_memory_pipeline.cc
M src/gpu-compute/gpu_command_processor.cc
M src/gpu-compute/gpu_command_processor.hh
M src/gpu-compute/gpu_compute_driver.cc
M src/gpu-compute/gpu_compute_driver.hh
M src/gpu-compute/gpu_dyn_inst.cc
M src/gpu-compute/gpu_dyn_inst.hh
M src/gpu-compute/gpu_exec_context.cc
M src/gpu-compute/gpu_static_inst.cc
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/hsa_queue_entry.hh
M src/gpu-compute/lds_state.cc
M src/gpu-compute/operand_info.hh
M src/gpu-compute/pool_manager.cc
M src/gpu-compute/scalar_memory_pipeline.cc
M src/gpu-compute/scalar_register_file.cc
M src/gpu-compute/schedule_stage.cc
M src/gpu-compute/scoreboard_check_stage.cc
M src/gpu-compute/shader.cc
M src/gpu-compute/simple_pool_manager.cc
M src/gpu-compute/tlb_coalescer.cc
M src/gpu-compute/vector_register_file.cc
M src/gpu-compute/wavefront.cc
M src/kern/linux/linux.cc
M src/learning_gem5/part2/goodbye_object.cc
M src/learning_gem5/part2/simple_cache.cc
M src/learning_gem5/part2/simple_memobj.cc
M src/learning_gem5/part3/MSI-cache.sm
M src/learning_gem5/part3/MSI-dir.sm
M src/mem/abstract_mem.cc
M src/mem/abstract_mem.hh
M src/mem/bridge.cc
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/cache.cc
M src/mem/cache/cache_blk.cc
M src/mem/cache/cache_blk.hh
M src/mem/cache/compressors/base.cc
M src/mem/cache/compressors/base_delta_impl.hh
M src/mem/cache/compressors/cpack.cc
M src/mem/cache/compressors/encoders/huffman.cc
M src/mem/cache/compressors/encoders/huffman.hh
M src/mem/cache/compressors/fpc.cc
M src/mem/cache/compressors/frequent_values.cc
M src/mem/cache/compressors/repeated_qwords.cc
M src/mem/cache/compressors/zero.cc
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/mshr_queue.cc
M src/mem/cache/noncoherent_cache.cc
M src/mem/cache/prefetch/access_map_pattern_matching.cc
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
M src/mem/cache/prefetch/indirect_memory.cc
M src/mem/cache/prefetch/irregular_stream_buffer.cc
M src/mem/cache/prefetch/pif.cc
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/signature_path.cc
M src/mem/cache/prefetch/signature_path_v2.cc
M src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc
M src/mem/cache/replacement_policies/brrip_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/lfu_rp.cc
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/random_rp.cc
M src/mem/cache/replacement_policies/second_chance_rp.cc
M src/mem/cache/replacement_policies/tree_plru_rp.cc
M src/mem/cache/replacement_policies/weighted_lru_rp.cc
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/compressed_tags.cc
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/indexing_policies/base.cc
M src/mem/cache/tags/sector_blk.cc
M src/mem/cache/tags/sector_tags.cc
M src/mem/cache/tags/super_blk.cc
M src/mem/cache/tags/tagged_entry.hh
M src/mem/cache/write_queue.cc
M src/mem/cache/write_queue_entry.cc
M src/mem/cache/write_queue_entry.hh
M src/mem/cfi_mem.cc
M src/mem/coherent_xbar.cc
M src/mem/comm_monitor.cc
M src/mem/drampower.cc
M src/mem/dramsim2.cc
M src/mem/dramsim2_wrapper.cc
M src/mem/dramsim3.cc
M src/mem/dramsim3_wrapper.cc
M src/mem/external_slave.cc
M src/mem/hmc_controller.cc
M src/mem/mem_checker.cc
M src/mem/mem_checker.hh
M src/mem/mem_checker_monitor.cc
M src/mem/mem_ctrl.cc
M src/mem/mem_interface.cc
M src/mem/noncoherent_xbar.cc
M src/mem/packet.cc
M src/mem/packet.hh
M src/mem/packet_access.hh
M src/mem/packet_queue.cc
M src/mem/page_table.cc
M src/mem/page_table.hh
M src/mem/physical.cc
M src/mem/port_proxy.cc
M src/mem/probes/mem_footprint.cc
M src/mem/protocol/atomic.cc
M src/mem/protocol/functional.cc
M src/mem/protocol/timing.cc
M src/mem/qos/mem_ctrl.cc
M src/mem/qos/mem_ctrl.hh
M src/mem/qos/mem_sink.cc
M src/mem/qos/policy.cc
M src/mem/qos/policy_pf.cc
M src/mem/request.hh
M src/mem/ruby/common/Address.cc
M src/mem/ruby/common/Consumer.cc
M src/mem/ruby/common/DataBlock.cc
M src/mem/ruby/common/DataBlock.hh
M src/mem/ruby/common/ExpectedMap.hh
M src/mem/ruby/common/Histogram.cc
M src/mem/ruby/common/NetDest.cc
M src/mem/ruby/common/NetDest.hh
M src/mem/ruby/common/Set.hh
M src/mem/ruby/common/SubBlock.cc
M src/mem/ruby/common/WriteMask.hh
M src/mem/ruby/network/MessageBuffer.cc
M src/mem/ruby/network/Network.cc
M src/mem/ruby/network/Topology.cc
M src/mem/ruby/network/fault_model/FaultModel.cc
M src/mem/ruby/network/garnet/GarnetLink.cc
M src/mem/ruby/network/garnet/GarnetNetwork.cc
M src/mem/ruby/network/garnet/InputUnit.cc
M src/mem/ruby/network/garnet/NetworkBridge.cc
M src/mem/ruby/network/garnet/NetworkInterface.cc
M src/mem/ruby/network/garnet/NetworkInterface.hh
M src/mem/ruby/network/garnet/NetworkLink.cc
M src/mem/ruby/network/garnet/OutVcState.cc
M src/mem/ruby/network/garnet/OutputUnit.cc
M src/mem/ruby/network/garnet/Router.cc
M src/mem/ruby/network/garnet/Router.hh
M src/mem/ruby/network/garnet/RoutingUnit.cc
M src/mem/ruby/network/garnet/SwitchAllocator.cc
M src/mem/ruby/network/garnet/VirtualChannel.cc
M src/mem/ruby/network/garnet/flit.cc
M src/mem/ruby/network/garnet/flit.hh
M src/mem/ruby/network/simple/PerfectSwitch.cc
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/Switch.cc
M src/mem/ruby/network/simple/Throttle.cc
M src/mem/ruby/profiler/AccessTraceForAddress.cc
M src/mem/ruby/profiler/StoreTrace.cc
M src/mem/ruby/protocol/GPU_VIPER-SQC.sm
M src/mem/ruby/protocol/GPU_VIPER-TCP.sm
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
M src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
M src/mem/ruby/protocol/MESI_Three_Level_HTM-L0cache.sm
M src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
M src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
M src/mem/ruby/protocol/MESI_Two_Level-dir.sm
M src/mem/ruby/protocol/MESI_Two_Level-dma.sm
M src/mem/ruby/protocol/MI_example-cache.sm
M src/mem/ruby/protocol/MI_example-dir.sm
M src/mem/ruby/protocol/MI_example-dma.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-L3cache.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-RegionBuffer.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-RegionDir.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-dma.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
M src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
M src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
M src/mem/ruby/protocol/MOESI_CMP_token-dir.sm
M src/mem/ruby/protocol/MOESI_CMP_token-dma.sm
M src/mem/ruby/protocol/MOESI_hammer-cache.sm
M src/mem/ruby/protocol/MOESI_hammer-dir.sm
M src/mem/ruby/protocol/MOESI_hammer-dma.sm
M src/mem/ruby/protocol/RubySlicc_Util.sm
M src/mem/ruby/protocol/chi/CHI-cache-actions.sm
M src/mem/ruby/protocol/chi/CHI-cache-funcs.sm
M src/mem/ruby/protocol/chi/CHI-cache-ports.sm
M src/mem/ruby/protocol/chi/CHI-mem.sm
M src/mem/ruby/protocol/chi/CHI-msg.sm
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/slicc_interface/Message.hh
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
M src/mem/ruby/structures/BankedArray.cc
M src/mem/ruby/structures/CacheMemory.cc
M src/mem/ruby/structures/DirectoryMemory.cc
M src/mem/ruby/structures/PerfectCacheMemory.hh
M src/mem/ruby/structures/PersistentTable.cc
M src/mem/ruby/structures/RubyPrefetcher.cc
M src/mem/ruby/structures/TBEStorage.hh
M src/mem/ruby/structures/TBETable.hh
M src/mem/ruby/structures/TimerTable.cc
M src/mem/ruby/structures/TimerTable.hh
M src/mem/ruby/structures/WireBuffer.cc
M src/mem/ruby/system/CacheRecorder.cc
M src/mem/ruby/system/DMASequencer.cc
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/HTMSequencer.cc
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubySystem.cc
M src/mem/ruby/system/RubySystem.hh
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
M src/mem/ruby/system/VIPERCoalescer.cc
M src/mem/serial_link.cc
M src/mem/simple_mem.cc
M src/mem/slicc/symbols/StateMachine.py
M src/mem/slicc/symbols/Type.py
M src/mem/snoop_filter.cc
M src/mem/snoop_filter.hh
M src/mem/tport.cc
M src/mem/xbar.cc
M src/proto/protoio.cc
M src/sim/clock_domain.cc
M src/sim/clock_domain.hh
M src/sim/drain.cc
M src/sim/dvfs_handler.cc
M src/sim/dvfs_handler.hh
M src/sim/eventq.cc
M src/sim/eventq.hh
M src/sim/faults.cc
M src/sim/fd_array.cc
M src/sim/global_event.hh
M src/sim/init.cc
M src/sim/insttracer.hh
M src/sim/linear_solver.hh
M src/sim/mem_state.cc
M src/sim/port.hh
M src/sim/power/mathexpr_powermodel.cc
M src/sim/power/power_model.cc
M src/sim/power/thermal_domain.cc
M src/sim/power_domain.cc
M src/sim/power_state.cc
M src/sim/process.cc
M src/sim/proxy_ptr.hh
M src/sim/root.cc
M src/sim/root.hh
M src/sim/serialize.cc
M src/sim/sim_events.cc
M src/sim/sim_object.cc
M src/sim/simulate.cc
M src/sim/syscall_emul.cc
M src/sim/syscall_return.hh
M src/sim/system.cc
M src/sim/system.hh
M src/sim/vma.cc
M src/sim/voltage_domain.hh
M util/m5/src/call_type.cc
M util/m5/src/call_type/addr.test.cc
M util/m5/src/command/writefile.test.cc
M util/m5/src/lua_gem5Op.cc
M util/tlm/src/sc_master_port.cc
M util/tlm/src/sc_peq.hh
M util/tlm/src/sc_slave_port.hh
M util/tlm/src/sim_control.cc
600 files changed, 6,572 insertions(+), 6,601 deletions(-)
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ide2718de8c987f6ab2bed084efc68f8aa75f17de
Gerrit-Change-Number: 45028
Gerrit-PatchSet: 1
Gerrit-Owner: Gabriel Busnot <garbage2collec...@gmail.com>
Gerrit-MessageType: newchange
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