Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45187 )
Change subject: arch-arm: Implement ARMv8.1-VMID16, 16-bit VMID
......................................................................
arch-arm: Implement ARMv8.1-VMID16, 16-bit VMID
In an Armv8.1 implementation, when EL2 is using AArch64, the VMID size
is an IMPLEMENTATION DEFINED choice of 8 bits or 16 bits.
When implemented, this feature is supported only when EL2 is using AArch64.
The ID_AA64MMFR1_EL1.VMIDBits field identifies the supported VMID size.
Change-Id: I7acde0a9ba285d4740771133debd60a7a7515954
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc_types.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
4 files changed, 39 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 80035ae..69a350f 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2177,6 +2177,7 @@
case MISCREG_TCR_EL1:
case MISCREG_TCR_EL2:
case MISCREG_TCR_EL3:
+ case MISCREG_VTCR_EL2:
case MISCREG_SCTLR_EL2:
case MISCREG_SCTLR_EL3:
case MISCREG_HSCTLR:
diff --git a/src/arch/arm/regs/misc_types.hh
b/src/arch/arm/regs/misc_types.hh
index c3fd06e..66b1809 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2020 ARM Limited
+ * Copyright (c) 2010-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -563,6 +563,7 @@
Bitfield<13, 12> sh0;
Bitfield<15, 14> tg0;
Bitfield<18, 16> ps; // Only defined for VTCR_EL2
+ Bitfield<19> vs; // Only defined for VTCR_EL2
Bitfield<21> ha; // Only defined for VTCR_EL2
Bitfield<22> hd; // Only defined for VTCR_EL2
EndBitUnion(VTCR_t)
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 789b29a..a117ebd 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013, 2016-2020 ARM Limited
+ * Copyright (c) 2010-2013, 2016-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -1372,6 +1372,35 @@
return &stage2Mmu->getDMAPort();
}
+uint16_t
+TLB::getVMID(ThreadContext *tc) const
+{
+ AA64MMFR1 mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
+ VTCR_t vtcr = tc->readMiscReg(MISCREG_VTCR_EL2);
+ uint16_t vmid = 0;
+
+ switch (mmfr1.vmidbits) {
+ case 0b0000:
+ // 8 bits
+ vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48);
+ break;
+ case 0b0010:
+ if (vtcr.vs && ELIs64(tc, EL2)) {
+ // 16 bits
+ vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 63, 48);
+ } else {
+ // 8 bits
+ vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48);
+ }
+ break;
+ default:
+ panic("Reserved ID_AA64MMFR1_EL1.VMIDBits value: %#x",
+ mmfr1.vmidbits);
+ }
+
+ return vmid;
+}
+
void
TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType)
{
@@ -1456,7 +1485,7 @@
scr = tc->readMiscReg(MISCREG_SCR_EL3);
isPriv = aarch64EL != EL0;
if (haveVirtualization) {
- vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48);
+ vmid = getVMID(tc);
isHyp = aarch64EL == EL2;
isHyp |= tranType & HypMode;
isHyp &= (tranType & S1S2NsTran) == 0;
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 6f0f75f..12a8a20 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013, 2016, 2019-2020 ARM Limited
+ * Copyright (c) 2010-2013, 2016, 2019-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -443,6 +443,10 @@
void updateMiscReg(ThreadContext *tc,
ArmTranslationType tranType = NormalTran);
+ /** Returns the current VMID
+ * (information stored in the VTTBR_EL2 register) */
+ uint16_t getVMID(ThreadContext *tc) const;
+
public:
void invalidateMiscReg() { miscRegValid = false; }
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7acde0a9ba285d4740771133debd60a7a7515954
Gerrit-Change-Number: 45187
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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