Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45391 )
Change subject: dev: Rename iGbReg namespace as igbreg
......................................................................
dev: Rename iGbReg namespace as igbreg
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.
::iGbReg became ::igbreg.
Change-Id: I4b19503c8cda37248667464be0ac4fd9a7bb42d8
Signed-off-by: Daniel R. Carvalho <oda...@yahoo.com.br>
---
M src/dev/net/i8254xGBe.cc
M src/dev/net/i8254xGBe.hh
M src/dev/net/i8254xGBe_defs.hh
3 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/src/dev/net/i8254xGBe.cc b/src/dev/net/i8254xGBe.cc
index 73bea7a..c5affcf 100644
--- a/src/dev/net/i8254xGBe.cc
+++ b/src/dev/net/i8254xGBe.cc
@@ -52,7 +52,7 @@
#include "sim/stats.hh"
#include "sim/system.hh"
-using namespace iGbReg;
+using namespace igbreg;
using namespace Net;
IGbE::IGbE(const Params &p)
@@ -1898,7 +1898,7 @@
{
DPRINTF(EthernetDesc, "actionAfterWb() completionEnabled: %d\n",
completionEnabled);
- igbe->postInterrupt(iGbReg::IT_TXDW);
+ igbe->postInterrupt(igbreg::IT_TXDW);
if (completionEnabled) {
descEnd = igbe->regs.tdh();
DPRINTF(EthernetDesc,
@@ -2365,7 +2365,7 @@
SERIALIZE_SCALAR(eeOpcode);
SERIALIZE_SCALAR(eeAddr);
SERIALIZE_SCALAR(lastInterrupt);
- SERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
+ SERIALIZE_ARRAY(flash,igbreg::EEPROM_SIZE);
rxFifo.serialize("rxfifo", cp);
txFifo.serialize("txfifo", cp);
@@ -2416,7 +2416,7 @@
UNSERIALIZE_SCALAR(eeOpcode);
UNSERIALIZE_SCALAR(eeAddr);
UNSERIALIZE_SCALAR(lastInterrupt);
- UNSERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
+ UNSERIALIZE_ARRAY(flash,igbreg::EEPROM_SIZE);
rxFifo.unserialize("rxfifo", cp);
txFifo.unserialize("txfifo", cp);
diff --git a/src/dev/net/i8254xGBe.hh b/src/dev/net/i8254xGBe.hh
index 6ae0cb3..2677528 100644
--- a/src/dev/net/i8254xGBe.hh
+++ b/src/dev/net/i8254xGBe.hh
@@ -60,12 +60,12 @@
IGbEInt *etherInt;
// device registers
- iGbReg::Regs regs;
+ igbreg::Regs regs;
// eeprom data, status and control bits
int eeOpBits, eeAddrBits, eeDataBits;
uint8_t eeOpcode, eeAddr;
- uint16_t flash[iGbReg::EEPROM_SIZE];
+ uint16_t flash[igbreg::EEPROM_SIZE];
// packet fifos
PacketFifo rxFifo;
@@ -95,7 +95,7 @@
rxDescCache.writeback(0);
DPRINTF(EthernetIntr,
"Posting RXT interrupt because RDTR timer expired\n");
- postInterrupt(iGbReg::IT_RXT);
+ postInterrupt(igbreg::IT_RXT);
}
EventFunctionWrapper rdtrEvent;
@@ -105,7 +105,7 @@
rxDescCache.writeback(0);
DPRINTF(EthernetIntr,
"Posting RXT interrupt because RADV timer expired\n");
- postInterrupt(iGbReg::IT_RXT);
+ postInterrupt(igbreg::IT_RXT);
}
EventFunctionWrapper radvEvent;
@@ -115,7 +115,7 @@
txDescCache.writeback(0);
DPRINTF(EthernetIntr,
"Posting TXDW interrupt because TADV timer expired\n");
- postInterrupt(iGbReg::IT_TXDW);
+ postInterrupt(igbreg::IT_TXDW);
}
EventFunctionWrapper tadvEvent;
@@ -125,7 +125,7 @@
txDescCache.writeback(0);
DPRINTF(EthernetIntr,
"Posting TXDW interrupt because TIDV timer expired\n");
- postInterrupt(iGbReg::IT_TXDW);
+ postInterrupt(igbreg::IT_TXDW);
}
EventFunctionWrapper tidvEvent;
@@ -145,7 +145,7 @@
* @param t the type of interrupt we are posting
* @param now should we ignore the interrupt limiting timer
*/
- void postInterrupt(iGbReg::IntTypes t, bool now = false);
+ void postInterrupt(igbreg::IntTypes t, bool now = false);
/** Check and see if changes to the mask register have caused an
interrupt
* to need to be sent or perhaps removed an interrupt cause.
@@ -299,7 +299,7 @@
};
- class RxDescCache : public DescCache<iGbReg::RxDesc>
+ class RxDescCache : public DescCache<igbreg::RxDesc>
{
protected:
Addr descBase() const override { return igbe->regs.rdba(); }
@@ -360,7 +360,7 @@
RxDescCache rxDescCache;
- class TxDescCache : public DescCache<iGbReg::TxDesc>
+ class TxDescCache : public DescCache<igbreg::TxDesc>
{
protected:
Addr descBase() const override { return igbe->regs.tdba(); }
@@ -418,7 +418,7 @@
unsigned
descInBlock(unsigned num_desc)
{
- return num_desc / igbe->cacheBlockSize() /
sizeof(iGbReg::TxDesc);
+ return num_desc / igbe->cacheBlockSize() /
sizeof(igbreg::TxDesc);
}
/** Ask if the packet has been transfered so the state machine can
give
diff --git a/src/dev/net/i8254xGBe_defs.hh b/src/dev/net/i8254xGBe_defs.hh
index 48610e2..90af3b4 100644
--- a/src/dev/net/i8254xGBe_defs.hh
+++ b/src/dev/net/i8254xGBe_defs.hh
@@ -32,8 +32,8 @@
#include "base/bitfield.hh"
#include "base/compiler.hh"
-namespace iGbReg {
-
+GEM5_DEPRECATED_NAMESPACE(iGbReg, igbreg);
+namespace igbreg {
// Registers used by the Intel GbE NIC
const uint32_t REG_CTRL = 0x00000;
@@ -938,4 +938,4 @@
UNSERIALIZE_SCALAR(sw_fw_sync);
}
};
-} // namespace iGbReg
+} // namespace igbreg
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4b19503c8cda37248667464be0ac4fd9a7bb42d8
Gerrit-Change-Number: 45391
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-MessageType: newchange
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