Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45524 )
Change subject: arch-riscv: Use operands instead of (read|set)MiscReg in
CSR ops.
......................................................................
arch-riscv: Use operands instead of (read|set)MiscReg in CSR ops.
Don't go behind the parsers back to access operands.
Change-Id: Ie6aa581ab355271301120a5c390152f7e6f8f667
---
M src/arch/riscv/isa/formats/standard.isa
M src/arch/riscv/isa/operands.isa
2 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index 23a02ff..648134f 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -464,13 +464,12 @@
}};
def format CSROp(code, *opt_flags) {{
- basic_read = "xc->readMiscReg(midx);"
- basic_write = "xc->setMiscReg(midx, data);"
+ basic_read = "Csr;"
+ basic_write = "Csr = data;"
satp_priv = """
- auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
- STATUS status = xc->readMiscReg(MISCREG_STATUS);
- if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) {
+ STATUS status = Status;
+ if (Prv == PRV_U || (Prv == PRV_S && status.tvm == 1)) {
return std::make_shared<IllegalInstFault>(
"SATP access in user mode or with TVM enabled\\n",
machInst);
@@ -478,21 +477,16 @@
"""
mstatus_priv = """
- auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
- if (pm != PrivilegeMode::PRV_M) {
+ if (Prv != PrivilegeMode::PRV_M) {
return std::make_shared<IllegalInstFault>(
- "MSTATUS is only accessibly in machine mode\\n",
- machInst);
+ "MSTATUS is only accessibly in machine mode\\n",
machInst);
}
"""
- fcsr_read = """
- xc->readMiscReg(MISCREG_FFLAGS) |
- (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
- """
+ fcsr_read = "Fflags | (Frm << FRM_OFFSET);"
fcsr_write = """
- xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4, 0));
- xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
+ Fflags = bits(data, 4, 0);
+ Frm = bits(data, 7, 5);
"""
regs = (
diff --git a/src/arch/riscv/isa/operands.isa
b/src/arch/riscv/isa/operands.isa
index 78cd5f9..959987d 100644
--- a/src/arch/riscv/isa/operands.isa
+++ b/src/arch/riscv/isa/operands.isa
@@ -38,7 +38,9 @@
'sd' : 'int64_t',
'ud' : 'uint64_t',
'sf' : 'float',
- 'df' : 'double'
+ 'df' : 'double',
+
+ 'status' : 'STATUS',
}};
def operands {{
@@ -74,6 +76,13 @@
#Memory Operand
'Mem': ('Mem', 'ud', None, (None, 'IsLoad', 'IsStore'), 5),
+#Misc Operands
+ 'Csr': ('ControlReg', 'ud', 'midx', None, 9),
+ 'Fflags': ('ControlReg', 'ud', 'MISCREG_FFLAGS', None, 10),
+ 'Frm': ('ControlReg', 'ud', 'MISCREG_FRM', None, 11),
+ 'Prv': ('ControlReg', 'ud', 'MISCREG_PRV', None, 12),
+ 'Status': ('ControlReg', 'status', 'MISCREG_STATUS', None, 13),
+
#Program Counter Operands
'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7),
'NPC': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 8),
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie6aa581ab355271301120a5c390152f7e6f8f667
Gerrit-Change-Number: 45524
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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