Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45527 )
Change subject: arch-riscv: Pull some code out of a macro and into the ISA
desc.
......................................................................
arch-riscv: Pull some code out of a macro and into the ISA desc.
A macro defined outside of the ISA description was pulled into the
description and used in the implementation of some instructions. Macros
are inherently not great, and this also hid any operands being used from
the ISA parser. This change also makes that code use an operand to read
FRM instead of calling readMiscReg directly.
Change-Id: If3ef7aeef8299f3a0dcc9d59f01414845ea2eb36
---
D src/arch/riscv/fp_inst.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/fp.isa
M src/arch/riscv/isa/includes.isa
4 files changed, 63 insertions(+), 118 deletions(-)
diff --git a/src/arch/riscv/fp_inst.hh b/src/arch/riscv/fp_inst.hh
deleted file mode 100644
index 604c016..0000000
--- a/src/arch/riscv/fp_inst.hh
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2021 StreamComputing Corp.
- * All rights reserved
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kai Ren
- */
-
-#ifndef __ARCH_RISCV_FP_INST_HH__
-#define __ARCH_RISCV_FP_INST_HH__
-
-#define
RM_REQUIRED \
- uint_fast8_t rm =
ROUND_MODE; \
- uint_fast8_t frm =
xc->readMiscReg(MISCREG_FRM); \
- if (rm ==
7) \
- rm =
frm; \
- if (rm >
4) \
- return std::make_shared<IllegalInstFault>("RM fault",
machInst);\
- softfloat_roundingMode =
rm; \
-
-#endif // __ARCH_RISCV_FP_INST_HH__
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 6482dd6..f5e69c0 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -887,16 +887,14 @@
format FPROp {
0x10: decode FUNCT2 {
- 0x0: fmadd_s({{
- RM_REQUIRED;
+ 0x0: FPROpRm::fmadd_s({{
freg_t fd;
fd = freg(f32_mulAdd(f32(freg(Fs1_bits)),
f32(freg(Fs2_bits)),
f32(freg(Fs3_bits))));
Fd_bits = fd.v;
}}, FloatMultAccOp);
- 0x1: fmadd_d({{
- RM_REQUIRED;
+ 0x1: FPROpRm::fmadd_d({{
freg_t fd;
fd = freg(f64_mulAdd(f64(freg(Fs1_bits)),
f64(freg(Fs2_bits)),
@@ -905,8 +903,7 @@
}}, FloatMultAccOp);
}
0x11: decode FUNCT2 {
- 0x0: fmsub_s({{
- RM_REQUIRED;
+ 0x0: FPROpRm::fmsub_s({{
freg_t fd;
fd = freg(f32_mulAdd(f32(freg(Fs1_bits)),
f32(freg(Fs2_bits)),
@@ -914,8 +911,7 @@
mask(31, 31))));
Fd_bits = fd.v;
}}, FloatMultAccOp);
- 0x1: fmsub_d({{
- RM_REQUIRED;
+ 0x1: FPROpRm::fmsub_d({{
freg_t fd;
fd = freg(f64_mulAdd(f64(freg(Fs1_bits)),
f64(freg(Fs2_bits)),
@@ -925,8 +921,7 @@
}}, FloatMultAccOp);
}
0x12: decode FUNCT2 {
- 0x0: fnmsub_s({{
- RM_REQUIRED;
+ 0x0: FPROpRm::fnmsub_s({{
freg_t fd;
fd = freg(f32_mulAdd(f32(f32(freg(Fs1_bits)).v ^
mask(31, 31)),
@@ -934,8 +929,7 @@
f32(freg(Fs3_bits))));
Fd_bits = fd.v;
}}, FloatMultAccOp);
- 0x1: fnmsub_d({{
- RM_REQUIRED;
+ 0x1: FPROpRm::fnmsub_d({{
freg_t fd;
fd = freg(f64_mulAdd(f64(f64(freg(Fs1_bits)).v ^
mask(63, 63)),
@@ -945,8 +939,7 @@
}}, FloatMultAccOp);
}
0x13: decode FUNCT2 {
- 0x0: fnmadd_s({{
- RM_REQUIRED;
+ 0x0: FPROpRm::fnmadd_s({{
freg_t fd;
fd = freg(f32_mulAdd(f32(f32(freg(Fs1_bits)).v ^
mask(31, 31)),
@@ -955,8 +948,7 @@
mask(31, 31))));
Fd_bits = fd.v;
}}, FloatMultAccOp);
- 0x1: fnmadd_d({{
- RM_REQUIRED;
+ 0x1: FPROpRm::fnmadd_d({{
freg_t fd;
fd = freg(f64_mulAdd(f64(f64(freg(Fs1_bits)).v ^
mask(63, 63)),
@@ -967,57 +959,49 @@
}}, FloatMultAccOp);
}
0x14: decode FUNCT7 {
- 0x0: fadd_s({{
- RM_REQUIRED;
+ 0x0: FPROpRm::fadd_s({{
freg_t fd;
fd = freg(f32_add(f32(freg(Fs1_bits)),
f32(freg(Fs2_bits))));
Fd_bits = fd.v;
}}, FloatAddOp);
- 0x1: fadd_d({{
- RM_REQUIRED;
+ 0x1: FPROpRm::fadd_d({{
freg_t fd;
fd = freg(f64_add(f64(freg(Fs1_bits)),
f64(freg(Fs2_bits))));
Fd_bits = fd.v;
}}, FloatAddOp);
- 0x4: fsub_s({{
- RM_REQUIRED;
+ 0x4: FPROpRm::fsub_s({{
freg_t fd;
fd = freg(f32_sub(f32(freg(Fs1_bits)),
f32(freg(Fs2_bits))));
Fd_bits = fd.v;
}}, FloatAddOp);
- 0x5: fsub_d({{
- RM_REQUIRED;
+ 0x5: FPROpRm::fsub_d({{
freg_t fd;
fd = freg(f64_sub(f64(freg(Fs1_bits)),
f64(freg(Fs2_bits))));
Fd_bits = fd.v;
}}, FloatAddOp);
- 0x8: fmul_s({{
- RM_REQUIRED;
+ 0x8: FPROpRm::fmul_s({{
freg_t fd;
fd = freg(f32_mul(f32(freg(Fs1_bits)),
f32(freg(Fs2_bits))));
Fd_bits = fd.v;
}}, FloatMultOp);
- 0x9: fmul_d({{
- RM_REQUIRED;
+ 0x9: FPROpRm::fmul_d({{
freg_t fd;
fd = freg(f64_mul(f64(freg(Fs1_bits)),
f64(freg(Fs2_bits))));
Fd_bits = fd.v;
}}, FloatMultOp);
- 0xc: fdiv_s({{
- RM_REQUIRED;
+ 0xc: FPROpRm::fdiv_s({{
freg_t fd;
fd = freg(f32_div(f32(freg(Fs1_bits)),
f32(freg(Fs2_bits))));
Fd_bits = fd.v;
}}, FloatDivOp);
- 0xd: fdiv_d({{
- RM_REQUIRED;
+ 0xd: FPROpRm::fdiv_d({{
freg_t fd;
fd = freg(f64_div(f64(freg(Fs1_bits)),
f64(freg(Fs2_bits))));
@@ -1111,43 +1095,39 @@
Fd_bits = f64(defaultNaNF64UI).v;
}}, FloatCmpOp);
}
- 0x20: fcvt_s_d({{
+ 0x20: FPROpRm::fcvt_s_d({{
if (CONV_SGN != 1) {
return std::make_shared<IllegalInstFault>(
"CONV_SGN != 1", machInst);
}
- RM_REQUIRED;
freg_t fd;
fd = freg(f64_to_f32(f64(freg(Fs1_bits))));
Fd_bits = fd.v;
}}, FloatCvtOp);
- 0x21: fcvt_d_s({{
+ 0x21: FPROpRm::fcvt_d_s({{
if (CONV_SGN != 0) {
return std::make_shared<IllegalInstFault>(
"CONV_SGN != 0", machInst);
}
- RM_REQUIRED;
freg_t fd;
fd = freg(f32_to_f64(f32(freg(Fs1_bits))));
Fd_bits = fd.v;
}}, FloatCvtOp);
- 0x2c: fsqrt_s({{
+ 0x2c: FPROpRm::fsqrt_s({{
if (RS2 != 0) {
return std::make_shared<IllegalInstFault>(
"source reg x1", machInst);
}
freg_t fd;
- RM_REQUIRED;
fd = freg(f32_sqrt(f32(freg(Fs1_bits))));
Fd_bits = fd.v;
}}, FloatSqrtOp);
- 0x2d: fsqrt_d({{
+ 0x2d: FPROpRm::fsqrt_d({{
if (RS2 != 0) {
return std::make_shared<IllegalInstFault>(
"source reg x1", machInst);
}
freg_t fd;
- RM_REQUIRED;
fd = freg(f64_sqrt(f64(freg(Fs1_bits))));
Fd_bits = fd.v;
}}, FloatSqrtOp);
@@ -1174,86 +1154,70 @@
}}, FloatCmpOp);
}
0x60: decode CONV_SGN {
- 0x0: fcvt_w_s({{
- RM_REQUIRED;
+ 0x0: FPROpRm::fcvt_w_s({{
Rd_sd = sext<32>(f32_to_i32(f32(freg(Fs1_bits)),
rm,
true));
}}, FloatCvtOp);
- 0x1: fcvt_wu_s({{
- RM_REQUIRED;
+ 0x1: FPROpRm::fcvt_wu_s({{
Rd = sext<32>(f32_to_ui32(f32(freg(Fs1_bits)), rm,
true));
}}, FloatCvtOp);
- 0x2: fcvt_l_s({{
- RM_REQUIRED;
+ 0x2: FPROpRm::fcvt_l_s({{
Rd_sd = f32_to_i64(f32(freg(Fs1_bits)), rm, true);
}}, FloatCvtOp);
- 0x3: fcvt_lu_s({{
- RM_REQUIRED;
+ 0x3: FPROpRm::fcvt_lu_s({{
Rd = f32_to_ui64(f32(freg(Fs1_bits)), rm, true);
}}, FloatCvtOp);
}
0x61: decode CONV_SGN {
- 0x0: fcvt_w_d({{
- RM_REQUIRED;
+ 0x0: FPROpRm::fcvt_w_d({{
Rd_sd = sext<32>(f64_to_i32(f64(freg(Fs1_bits)),
rm,
true));
}}, FloatCvtOp);
- 0x1: fcvt_wu_d({{
- RM_REQUIRED;
+ 0x1: FPROpRm::fcvt_wu_d({{
Rd = sext<32>(f64_to_ui32(f64(freg(Fs1_bits)), rm,
true));
}}, FloatCvtOp);
- 0x2: fcvt_l_d({{
- RM_REQUIRED;
+ 0x2: FPROpRm::fcvt_l_d({{
Rd_sd = f64_to_i64(f64(freg(Fs1_bits)), rm, true);
}}, FloatCvtOp);
- 0x3: fcvt_lu_d({{
- RM_REQUIRED;
+ 0x3: FPROpRm::fcvt_lu_d({{
Rd = f64_to_ui64(f64(freg(Fs1_bits)), rm, true);
}}, FloatCvtOp);
}
0x68: decode CONV_SGN {
- 0x0: fcvt_s_w({{
- RM_REQUIRED;
+ 0x0: FPROpRm::fcvt_s_w({{
freg_t fd;
fd = freg(i32_to_f32((int32_t)Rs1_sw));
Fd_bits = fd.v;
}}, FloatCvtOp);
- 0x1: fcvt_s_wu({{
- RM_REQUIRED;
+ 0x1: FPROpRm::fcvt_s_wu({{
freg_t fd;
fd = freg(ui32_to_f32((int32_t)Rs1_uw));
Fd_bits = fd.v;
}}, FloatCvtOp);
- 0x2: fcvt_s_l({{
- RM_REQUIRED;
+ 0x2: FPROpRm::fcvt_s_l({{
freg_t fd;
fd = freg(i64_to_f32(Rs1_ud));
Fd_bits = fd.v;
}}, FloatCvtOp);
- 0x3: fcvt_s_lu({{
- RM_REQUIRED;
+ 0x3: FPROpRm::fcvt_s_lu({{
freg_t fd;
fd = freg(ui64_to_f32(Rs1));
Fd_bits = fd.v;
}}, FloatCvtOp);
}
0x69: decode CONV_SGN {
- 0x0: fcvt_d_w({{
- RM_REQUIRED;
+ 0x0: FPROpRm::fcvt_d_w({{
Fd = (double)Rs1_sw;
}}, FloatCvtOp);
- 0x1: fcvt_d_wu({{
- RM_REQUIRED;
+ 0x1: FPROpRm::fcvt_d_wu({{
Fd = (double)Rs1_uw;
}}, FloatCvtOp);
- 0x2: fcvt_d_l({{
- RM_REQUIRED;
+ 0x2: FPROpRm::fcvt_d_l({{
Fd = (double)Rs1_sd;
}}, FloatCvtOp);
- 0x3: fcvt_d_lu({{
- RM_REQUIRED;
+ 0x3: FPROpRm::fcvt_d_lu({{
Fd = (double)Rs1;
}}, FloatCvtOp);
}
diff --git a/src/arch/riscv/isa/formats/fp.isa
b/src/arch/riscv/isa/formats/fp.isa
index 9f0ad20..5881781 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -41,6 +41,7 @@
%(op_rd)s;
std::feclearexcept(FE_ALL_EXCEPT);
+ %(rounding_mode)s;
%(code)s;
%(set_fflags)s;
@@ -50,7 +51,7 @@
}
}};
-def format FPROp(code, *opt_flags) {{
+let {{
fp_enabled_check = """
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
@@ -61,11 +62,35 @@
Fflags = Fflags | softfloat_exceptionFlags;
softfloat_exceptionFlags = 0;
"""
+}};
+
+def format FPROp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'RegOp',
+ { "code": code,
+ "fp_enabled_check": fp_enabled_check,
+ "set_fflags": set_fflags,
+ "rounding_mode": "" }, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = FloatExecute.subst(iop)
+}};
+
+def format FPROpRm(code, *opt_flags) {{
+ rounding_mode = """
+ auto rm = ROUND_MODE;
+ if (rm == 7)
+ rm = Frm;
+ if (rm > 4)
+ return std::make_shared<IllegalInstFault>("RM fault",
machInst);
+ softfloat_roundingMode = rm;
+ """
iop = InstObjParams(name, Name, 'RegOp',
{ "code": code,
"fp_enabled_check": fp_enabled_check,
- "set_fflags": set_fflags }, opt_flags)
+ "set_fflags": set_fflags,
+ "rounding_mode": rounding_mode }, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index 2f97f15..8b9b037 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -85,7 +85,6 @@
#include "arch/generic/memhelpers.hh"
#include "arch/riscv/faults.hh"
-#include "arch/riscv/fp_inst.hh"
#include "arch/riscv/mmu.hh"
#include "arch/riscv/reg_abi.hh"
#include "arch/riscv/regs/float.hh"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If3ef7aeef8299f3a0dcc9d59f01414845ea2eb36
Gerrit-Change-Number: 45527
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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