Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/45436 )
Change subject: sim,misc: Rename Int namespace as as_int
......................................................................
sim,misc: Rename Int namespace as as_int
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.
sim_clock::Int became sim_clock::as_int.
"as_int" was chosen because "int" is a reserved
keyword, and this namespace acts as a selector of
how to read the internal variables.
Another possibility to resolve this would be to
remove the namespaces "Float" and "Int" and use
unions instead.
Change-Id: I65f47608d2212424bed1731c7f53d242d5a7d89a
Signed-off-by: Daniel R. Carvalho <oda...@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45436
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Hoa Nguyen <hoangu...@ucdavis.edu>
Maintainer: Gabe Black <gabe.bl...@gmail.com>
---
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
M src/arch/arm/semihosting.cc
M src/dev/arm/energy_ctrl.cc
M src/dev/arm/energy_ctrl.hh
M src/dev/arm/rtc_pl031.cc
M src/dev/mc146818.cc
M src/dev/mc146818.hh
M src/dev/net/etherdump.cc
M src/dev/net/etherswitch.cc
M src/dev/net/ethertap.cc
M src/dev/net/i8254xGBe.cc
M src/dev/net/i8254xGBe.hh
M src/dev/net/ns_gige.cc
M src/dev/serial/uart8250.cc
M src/gpu-compute/gpu_compute_driver.cc
M src/kern/freebsd/events.cc
M src/kern/linux/events.cc
M src/mem/cache/tags/base.cc
M src/mem/drampower.cc
M src/mem/dramsim2.cc
M src/mem/dramsim3.cc
M src/mem/xbar.cc
M src/sim/core.cc
M src/sim/core.hh
M src/sim/power/thermal_model.cc
M src/sim/pseudo_inst.cc
M src/sim/syscall_emul.hh
M src/systemc/tlm_bridge/tlm_to_gem5.cc
30 files changed, 68 insertions(+), 62 deletions(-)
Approvals:
Hoa Nguyen: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc
b/src/arch/arm/fastmodel/CortexA76/evs.cc
index 07bce7e..5b88077 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -42,7 +42,7 @@
void
ScxEvsCortexA76<Types>::setClkPeriod(Tick clk_period)
{
- clockRateControl->set_mul_div(sim_clock::Int::s, clk_period);
+ clockRateControl->set_mul_div(sim_clock::as_int::s, clk_period);
}
template <class Types>
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc
b/src/arch/arm/fastmodel/CortexR52/evs.cc
index 6260584..0e1b745 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -41,7 +41,7 @@
void
ScxEvsCortexR52<Types>::setClkPeriod(Tick clk_period)
{
- clockRateControl->set_mul_div(sim_clock::Int::s, clk_period);
+ clockRateControl->set_mul_div(sim_clock::as_int::s, clk_period);
}
template <class Types>
diff --git a/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
b/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
index d1281c8..354dc28 100644
--- a/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
+++ b/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
@@ -256,7 +256,7 @@
PL330::start_of_simulation()
{
// Set the clock rate using the divider inside the EVS.
- clockRateControl->set_mul_div(sim_clock::Int::s, clockPeriod);
+ clockRateControl->set_mul_div(sim_clock::as_int::s, clockPeriod);
}
} // namespace fastmodel
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 4ccf328..13038f0 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -500,7 +500,7 @@
ArmSemihosting::RetErrno
ArmSemihosting::callClock(ThreadContext *tc)
{
- return retOK(curTick() / (sim_clock::Int::s / 100));
+ return retOK(curTick() / (sim_clock::as_int::s / 100));
}
ArmSemihosting::RetErrno
diff --git a/src/dev/arm/energy_ctrl.cc b/src/dev/arm/energy_ctrl.cc
index 9df4dda..b03a394 100644
--- a/src/dev/arm/energy_ctrl.cc
+++ b/src/dev/arm/energy_ctrl.cc
@@ -99,7 +99,7 @@
break;
case DVFS_HANDLER_TRANS_LATENCY:
// Return transition latency in nanoseconds
- result = dvfsHandler->transLatency() / sim_clock::Int::ns;
+ result = dvfsHandler->transLatency() / sim_clock::as_int::ns;
DPRINTF(EnergyCtrl, "reading dvfs handler trans latency %d ns\n",
result);
break;
diff --git a/src/dev/arm/energy_ctrl.hh b/src/dev/arm/energy_ctrl.hh
index a68a55e..8a15b6c 100644
--- a/src/dev/arm/energy_ctrl.hh
+++ b/src/dev/arm/energy_ctrl.hh
@@ -164,7 +164,7 @@
uint32_t perfLevelToRead;
static uint32_t ticksTokHz(Tick period) {
- return (uint32_t)(sim_clock::Int::ms / period);
+ return (uint32_t)(sim_clock::as_int::ms / period);
}
static uint32_t toMicroVolt(double voltage) {
diff --git a/src/dev/arm/rtc_pl031.cc b/src/dev/arm/rtc_pl031.cc
index 3597936..6f4aa88 100644
--- a/src/dev/arm/rtc_pl031.cc
+++ b/src/dev/arm/rtc_pl031.cc
@@ -69,7 +69,8 @@
switch (daddr) {
case DataReg:
- data = timeVal + ((curTick() - lastWrittenTick) /
sim_clock::Int::s);
+ data = timeVal +
+ ((curTick() - lastWrittenTick) / sim_clock::as_int::s);
break;
case MatchReg:
data = matchVal;
@@ -154,7 +155,7 @@
timeVal);
uint32_t seconds_until = matchVal - timeVal;
- Tick ticks_until = sim_clock::Int::s * seconds_until;
+ Tick ticks_until = sim_clock::as_int::s * seconds_until;
if (matchEvent.scheduled()) {
DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");
diff --git a/src/dev/mc146818.cc b/src/dev/mc146818.cc
index 4cd5e97..0bc52fc 100644
--- a/src/dev/mc146818.cc
+++ b/src/dev/mc146818.cc
@@ -175,7 +175,7 @@
// from reset to active. So, we simply schedule the
// tick after 0.5s.
assert(!tickEvent.scheduled());
- schedule(tickEvent, curTick() + sim_clock::Int::s / 2);
+ schedule(tickEvent, curTick() + sim_clock::as_int::s /
2);
}
} break;
case RTC_STAT_REGB:
@@ -333,7 +333,7 @@
MC146818::RTCTickEvent::process()
{
DPRINTF(MC146818, "RTC clock tick\n");
- parent->schedule(this, curTick() + sim_clock::Int::s);
+ parent->schedule(this, curTick() + sim_clock::as_int::s);
parent->tickClock();
}
diff --git a/src/dev/mc146818.hh b/src/dev/mc146818.hh
index bf9f59e..b5e895f 100644
--- a/src/dev/mc146818.hh
+++ b/src/dev/mc146818.hh
@@ -70,7 +70,7 @@
Tick offset;
RTCTickEvent(MC146818 * _parent) :
- parent(_parent), offset(sim_clock::Int::s)
+ parent(_parent), offset(sim_clock::as_int::s)
{}
/** Event process to occur at interrupt*/
diff --git a/src/dev/net/etherdump.cc b/src/dev/net/etherdump.cc
index f82fded..4aa40e3 100644
--- a/src/dev/net/etherdump.cc
+++ b/src/dev/net/etherdump.cc
@@ -94,8 +94,8 @@
EtherDump::dumpPacket(EthPacketPtr &packet)
{
pcap_pkthdr pkthdr;
- pkthdr.seconds = curTick() / sim_clock::Int::s;
- pkthdr.microseconds = (curTick() / sim_clock::Int::us) % 1000000ULL;
+ pkthdr.seconds = curTick() / sim_clock::as_int::s;
+ pkthdr.microseconds = (curTick() / sim_clock::as_int::us) % 1000000ULL;
pkthdr.caplen = std::min(packet->length, maxlen);
pkthdr.len = packet->length;
stream->write(reinterpret_cast<char *>(&pkthdr), sizeof(pkthdr));
diff --git a/src/dev/net/etherswitch.cc b/src/dev/net/etherswitch.cc
index 13439f8..27fbc78 100644
--- a/src/dev/net/etherswitch.cc
+++ b/src/dev/net/etherswitch.cc
@@ -182,7 +182,7 @@
if (!sendPacket(outputFifo.front())) {
DPRINTF(Ethernet, "output port busy...retry later\n");
if (!txEvent.scheduled())
- parent->schedule(txEvent, curTick() + sim_clock::Int::ns);
+ parent->schedule(txEvent, curTick() + sim_clock::as_int::ns);
} else {
DPRINTF(Ethernet, "packet sent: len=%d\n",
outputFifo.front()->length);
outputFifo.pop();
diff --git a/src/dev/net/ethertap.cc b/src/dev/net/ethertap.cc
index d5ffdd1..d5e2984 100644
--- a/src/dev/net/ethertap.cc
+++ b/src/dev/net/ethertap.cc
@@ -194,7 +194,7 @@
DPRINTF(Ethernet, "bus busy...buffer for retransmission\n");
packetBuffer.push(packet);
if (!txEvent.scheduled())
- schedule(txEvent, curTick() + sim_clock::Int::ns);
+ schedule(txEvent, curTick() + sim_clock::as_int::ns);
} else if (dump) {
dump->dump(packet);
}
@@ -216,7 +216,7 @@
}
if (!packetBuffer.empty() && !txEvent.scheduled())
- schedule(txEvent, curTick() + sim_clock::Int::ns);
+ schedule(txEvent, curTick() + sim_clock::as_int::ns);
}
diff --git a/src/dev/net/i8254xGBe.cc b/src/dev/net/i8254xGBe.cc
index 88cd0d5..34a1e7e 100644
--- a/src/dev/net/i8254xGBe.cc
+++ b/src/dev/net/i8254xGBe.cc
@@ -699,7 +699,7 @@
regs.icr = regs.icr() | t;
- Tick itr_interval = sim_clock::Int::ns * 256 * regs.itr.interval();
+ Tick itr_interval = sim_clock::as_int::ns * 256 * regs.itr.interval();
DPRINTF(EthernetIntr,
"EINT: postInterrupt() curTick(): %d itr: %d interval: %d\n",
curTick(), regs.itr.interval(), itr_interval);
@@ -808,7 +808,7 @@
"Possibly scheduling interrupt because of imr
write\n");
if (!interEvent.scheduled()) {
Tick t = curTick() +
- sim_clock::Int::ns * 256 * regs.itr.interval();
+ sim_clock::as_int::ns * 256 * regs.itr.interval();
DPRINTF(Ethernet, "Scheduling for %d\n", t);
schedule(interEvent, t);
}
diff --git a/src/dev/net/i8254xGBe.hh b/src/dev/net/i8254xGBe.hh
index b9aa200..dfefd73 100644
--- a/src/dev/net/i8254xGBe.hh
+++ b/src/dev/net/i8254xGBe.hh
@@ -163,7 +163,7 @@
*/
void cpuClearInt();
- Tick intClock() { return sim_clock::Int::ns * 1024; }
+ Tick intClock() { return sim_clock::as_int::ns * 1024; }
/** This function is used to restart the clock so it can handle things
like
* draining and resume in one place. */
diff --git a/src/dev/net/ns_gige.cc b/src/dev/net/ns_gige.cc
index a350762..6d1313d 100644
--- a/src/dev/net/ns_gige.cc
+++ b/src/dev/net/ns_gige.cc
@@ -1395,7 +1395,7 @@
if (!txFifo.empty() && !txEvent.scheduled()) {
DPRINTF(Ethernet, "reschedule transmit\n");
- schedule(txEvent, curTick() + sim_clock::Int::ns);
+ schedule(txEvent, curTick() + sim_clock::as_int::ns);
}
}
diff --git a/src/dev/serial/uart8250.cc b/src/dev/serial/uart8250.cc
index 734a8fd..bced0e2 100644
--- a/src/dev/serial/uart8250.cc
+++ b/src/dev/serial/uart8250.cc
@@ -72,7 +72,7 @@
void
Uart8250::scheduleIntr(Event *event)
{
- static const Tick interval = 225 * sim_clock::Int::ns;
+ static const Tick interval = 225 * sim_clock::as_int::ns;
DPRINTF(Uart, "Scheduling IER interrupt for %s, at cycle %lld\n",
event->name(), curTick() + interval);
if (!event->scheduled())
@@ -179,7 +179,7 @@
if (ier.thri) {
DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
- if (curTick() - lastTxInt > 225 * sim_clock::Int::ns) {
+ if (curTick() - lastTxInt > 225 * sim_clock::as_int::ns) {
DPRINTF(Uart, "-- Interrupting Immediately... %d,%d\n",
curTick(), lastTxInt);
txIntrEvent.process();
diff --git a/src/gpu-compute/gpu_compute_driver.cc
b/src/gpu-compute/gpu_compute_driver.cc
index 18793fc..d23aede 100644
--- a/src/gpu-compute/gpu_compute_driver.cc
+++ b/src/gpu-compute/gpu_compute_driver.cc
@@ -284,7 +284,7 @@
* Derive all clock counters based on the tick. All
* device clocks are identical and perfectly in sync.
*/
- uint64_t elapsed_nsec = curTick() / sim_clock::Int::ns;
+ uint64_t elapsed_nsec = curTick() / sim_clock::as_int::ns;
args->gpu_clock_counter = elapsed_nsec;
args->cpu_clock_counter = elapsed_nsec;
args->system_clock_counter = elapsed_nsec;
diff --git a/src/kern/freebsd/events.cc b/src/kern/freebsd/events.cc
index 08b938b..e8b4be8 100644
--- a/src/kern/freebsd/events.cc
+++ b/src/kern/freebsd/events.cc
@@ -58,7 +58,7 @@
// time to 0 with the assumption that quiesce will not happen. To avoid
// the quiesce handling in this case, only execute the quiesce if time
0.
if (time > 0)
- tc->quiesceTick(curTick() + sim_clock::Int::ns * time);
+ tc->quiesceTick(curTick() + sim_clock::as_int::ns * time);
}
} // namespace free_bsd
diff --git a/src/kern/linux/events.cc b/src/kern/linux/events.cc
index 10680b5..2d5d500 100644
--- a/src/kern/linux/events.cc
+++ b/src/kern/linux/events.cc
@@ -91,7 +91,7 @@
// time to 0 with the assumption that quiesce will not happen. To avoid
// the quiesce handling in this case, only execute the quiesce if time
0.
if (time > 0)
- tc->quiesceTick(curTick() + sim_clock::Int::ns * time);
+ tc->quiesceTick(curTick() + sim_clock::as_int::ns * time);
}
} // namespace linux
diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index 27f557e..eec7e40 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -167,13 +167,13 @@
Tick age = blk.getAge();
int age_index;
- if (age / sim_clock::Int::us < 10) { // <10us
+ if (age / sim_clock::as_int::us < 10) { // <10us
age_index = 0;
- } else if (age / sim_clock::Int::us < 100) { // <100us
+ } else if (age / sim_clock::as_int::us < 100) { // <100us
age_index = 1;
- } else if (age / sim_clock::Int::ms < 1) { // <1ms
+ } else if (age / sim_clock::as_int::ms < 1) { // <1ms
age_index = 2;
- } else if (age / sim_clock::Int::ms < 10) { // <10ms
+ } else if (age / sim_clock::as_int::ms < 10) { // <10ms
age_index = 3;
} else
age_index = 4; // >10ms
diff --git a/src/mem/drampower.cc b/src/mem/drampower.cc
index 887dc5e..1656892 100644
--- a/src/mem/drampower.cc
+++ b/src/mem/drampower.cc
@@ -93,7 +93,7 @@
timingSpec.XSDLL = divCeil(p.tXSDLL, p.tCK);
// Clock period in ns
- timingSpec.clkPeriod = (p.tCK / (double)(sim_clock::Int::ns));
+ timingSpec.clkPeriod = (p.tCK / (double)(sim_clock::as_int::ns));
assert(timingSpec.clkPeriod != 0);
timingSpec.clkMhz = (1 / timingSpec.clkPeriod) * 1000;
return timingSpec;
diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc
index f896912..98bc70f 100644
--- a/src/mem/dramsim2.cc
+++ b/src/mem/dramsim2.cc
@@ -145,7 +145,7 @@
}
schedule(tickEvent,
- curTick() + wrapper.clockPeriod() * sim_clock::Int::ns);
+ curTick() + wrapper.clockPeriod() * sim_clock::as_int::ns);
}
Tick
@@ -284,7 +284,7 @@
void DRAMSim2::readComplete(unsigned id, uint64_t addr, uint64_t cycle)
{
assert(cycle == divCeil(curTick() - startTick,
- wrapper.clockPeriod() * sim_clock::Int::ns));
+ wrapper.clockPeriod() *
sim_clock::as_int::ns));
DPRINTF(DRAMSim2, "Read to address %lld complete\n", addr);
@@ -312,7 +312,7 @@
void DRAMSim2::writeComplete(unsigned id, uint64_t addr, uint64_t cycle)
{
assert(cycle == divCeil(curTick() - startTick,
- wrapper.clockPeriod() * sim_clock::Int::ns));
+ wrapper.clockPeriod() *
sim_clock::as_int::ns));
DPRINTF(DRAMSim2, "Write to address %lld complete\n", addr);
diff --git a/src/mem/dramsim3.cc b/src/mem/dramsim3.cc
index ecf33f3..480da7f 100644
--- a/src/mem/dramsim3.cc
+++ b/src/mem/dramsim3.cc
@@ -147,7 +147,7 @@
}
schedule(tickEvent,
- curTick() + wrapper.clockPeriod() * sim_clock::Int::ns);
+ curTick() + wrapper.clockPeriod() * sim_clock::as_int::ns);
}
Tick
diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc
index 45f8e1b..5c99cc5 100644
--- a/src/mem/xbar.cc
+++ b/src/mem/xbar.cc
@@ -117,7 +117,7 @@
// do a quick sanity check to ensure the timings are not being
// ignored, note that this specific value may cause problems for
// slower interconnects
- panic_if(pkt->headerDelay > sim_clock::Int::us,
+ panic_if(pkt->headerDelay > sim_clock::as_int::us,
"Encountered header delay exceeding 1 us\n");
if (pkt->hasData()) {
diff --git a/src/sim/core.cc b/src/sim/core.cc
index a870868..d0d0376 100644
--- a/src/sim/core.cc
+++ b/src/sim/core.cc
@@ -59,7 +59,9 @@
double GHz;
} // namespace as_float
-namespace Int {
+GEM5_DEPRECATED_NAMESPACE(Int, as_int);
+namespace as_int
+{
Tick s;
Tick ms;
Tick us;
@@ -97,11 +99,11 @@
as_float::MHz = 1.0 / as_float::us;
as_float::GHz = 1.0 / as_float::ns;
- Int::s = Frequency;
- Int::ms = Int::s / 1000;
- Int::us = Int::ms / 1000;
- Int::ns = Int::us / 1000;
- Int::ps = Int::ns / 1000;
+ as_int::s = Frequency;
+ as_int::ms = as_int::s / 1000;
+ as_int::us = as_int::ms / 1000;
+ as_int::ns = as_int::us / 1000;
+ as_int::ps = as_int::ns / 1000;
cprintf("Global frequency set at %d ticks per second\n",
_ticksPerSecond);
diff --git a/src/sim/core.hh b/src/sim/core.hh
index df47727..66f3fca 100644
--- a/src/sim/core.hh
+++ b/src/sim/core.hh
@@ -81,14 +81,16 @@
*
* @{
*/
-namespace Int {
+GEM5_DEPRECATED_NAMESPACE(Int, as_int);
+namespace as_int
+{
extern Tick s; ///< second
extern Tick ms; ///< millisecond
extern Tick us; ///< microsecond
extern Tick ns; ///< nanosecond
extern Tick ps; ///< picosecond
/** @} */
-} // namespace Int
+} // namespace as_int
} // namespace sim_clock
/** @} */
diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index 9ecbae9..8f92c6f 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -166,7 +166,7 @@
eq_nodes[i]->temp = Temperature::fromKelvin(temps[i]);
// Schedule next computation
- schedule(stepEvent, curTick() + sim_clock::Int::s * _step);
+ schedule(stepEvent, curTick() + sim_clock::as_int::s * _step);
// Notify everybody
for (auto dom : domains)
@@ -203,7 +203,7 @@
eq_nodes[i]->id = i;
// Schedule first thermal update
- schedule(stepEvent, curTick() + sim_clock::Int::s * _step);
+ schedule(stepEvent, curTick() + sim_clock::as_int::s * _step);
}
void
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 11f94f4..a5cba8e 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -127,7 +127,7 @@
quiesceNs(ThreadContext *tc, uint64_t ns)
{
DPRINTF(PseudoInst, "pseudo_inst::quiesceNs(%i)\n", ns);
- tc->quiesceTick(curTick() + sim_clock::Int::ns * ns);
+ tc->quiesceTick(curTick() + sim_clock::as_int::ns * ns);
}
void
@@ -143,14 +143,14 @@
DPRINTF(PseudoInst, "pseudo_inst::quiesceTime()\n");
return (tc->readLastActivate() - tc->readLastSuspend()) /
- sim_clock::Int::ns;
+ sim_clock::as_int::ns;
}
uint64_t
rpns(ThreadContext *tc)
{
DPRINTF(PseudoInst, "pseudo_inst::rpns()\n");
- return curTick() / sim_clock::Int::ns;
+ return curTick() / sim_clock::as_int::ns;
}
void
@@ -175,7 +175,7 @@
{
DPRINTF(PseudoInst, "pseudo_inst::m5exit(%i)\n", delay);
if (DistIface::readyToExit(delay)) {
- Tick when = curTick() + delay * sim_clock::Int::ns;
+ Tick when = curTick() + delay * sim_clock::as_int::ns;
exitSimLoop("m5_exit instruction encountered", 0, when, 0, true);
}
}
@@ -194,7 +194,7 @@
m5fail(ThreadContext *tc, Tick delay, uint64_t code)
{
DPRINTF(PseudoInst, "pseudo_inst::m5fail(%i, %i)\n", delay, code);
- Tick when = curTick() + delay * sim_clock::Int::ns;
+ Tick when = curTick() + delay * sim_clock::as_int::ns;
exitSimLoop("m5_fail instruction encountered", code, when, 0, true);
}
@@ -305,8 +305,8 @@
return;
- Tick when = curTick() + delay * sim_clock::Int::ns;
- Tick repeat = period * sim_clock::Int::ns;
+ Tick when = curTick() + delay * sim_clock::as_int::ns;
+ Tick repeat = period * sim_clock::as_int::ns;
Stats::schedStatEvent(false, true, when, repeat);
}
@@ -319,8 +319,8 @@
return;
- Tick when = curTick() + delay * sim_clock::Int::ns;
- Tick repeat = period * sim_clock::Int::ns;
+ Tick when = curTick() + delay * sim_clock::as_int::ns;
+ Tick repeat = period * sim_clock::as_int::ns;
Stats::schedStatEvent(true, false, when, repeat);
}
@@ -334,8 +334,8 @@
return;
- Tick when = curTick() + delay * sim_clock::Int::ns;
- Tick repeat = period * sim_clock::Int::ns;
+ Tick when = curTick() + delay * sim_clock::as_int::ns;
+ Tick repeat = period * sim_clock::as_int::ns;
Stats::schedStatEvent(true, true, when, repeat);
}
@@ -348,8 +348,8 @@
return;
if (DistIface::readyToCkpt(delay, period)) {
- Tick when = curTick() + delay * sim_clock::Int::ns;
- Tick repeat = period * sim_clock::Int::ns;
+ Tick when = curTick() + delay * sim_clock::as_int::ns;
+ Tick repeat = period * sim_clock::as_int::ns;
exitSimLoop("checkpoint", 0, when, repeat);
}
}
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 647c8a3..a91cd72 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -519,7 +519,7 @@
{
static const int OneMillion = 1000 * 1000;
- uint64_t elapsed_usecs = curTick() / sim_clock::Int::us;
+ uint64_t elapsed_usecs = curTick() / sim_clock::as_int::us;
sec = elapsed_usecs / OneMillion;
usec = elapsed_usecs % OneMillion;
}
@@ -532,7 +532,7 @@
{
static const int OneBillion = 1000 * 1000 * 1000;
- uint64_t elapsed_nsecs = curTick() / sim_clock::Int::ns;
+ uint64_t elapsed_nsecs = curTick() / sim_clock::as_int::ns;
sec = elapsed_nsecs / OneBillion;
nsec = elapsed_nsecs % OneBillion;
}
@@ -2102,7 +2102,7 @@
timesFunc(SyscallDesc *desc, ThreadContext *tc, VPtr<typename OS::tms>
bufp)
{
// Fill in the time structure (in clocks)
- int64_t clocks = curTick() * OS::M5_SC_CLK_TCK / sim_clock::Int::s;
+ int64_t clocks = curTick() * OS::M5_SC_CLK_TCK / sim_clock::as_int::s;
bufp->tms_utime = clocks;
bufp->tms_stime = 0;
bufp->tms_cutime = 0;
diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc
b/src/systemc/tlm_bridge/tlm_to_gem5.cc
index 1a35ff0..23a2358 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.cc
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc
@@ -341,7 +341,8 @@
"Packet sending failed!\n");
auto delay =
- sc_core::sc_time((double)(ticks / sim_clock::Int::ps),
sc_core::SC_PS);
+ sc_core::sc_time((double)(ticks / sim_clock::as_int::ps),
+ sc_core::SC_PS);
// update time
t += delay;
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45436
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I65f47608d2212424bed1731c7f53d242d5a7d89a
Gerrit-Change-Number: 45436
Gerrit-PatchSet: 9
Gerrit-Owner: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-Reviewer: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Hoa Nguyen <hoangu...@ucdavis.edu>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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