Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46120 )
Change subject: fastmodel: Fix building with Fast Model.
......................................................................
fastmodel: Fix building with Fast Model.
Some build errors had crept in over time. This change fixes them.
Change-Id: I457d32190aa65b0ecd2d6de3f4f5d42d922ae5d5
---
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/GIC/gic.cc
M src/arch/arm/fastmodel/GIC/gic.hh
M src/arch/arm/fastmodel/iris/isa.cc
M src/arch/arm/fastmodel/iris/isa.hh
M src/arch/arm/fastmodel/iris/thread_context.cc
M src/arch/arm/fastmodel/iris/thread_context.hh
7 files changed, 36 insertions(+), 22 deletions(-)
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index 43510e6..98c2922 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -28,6 +28,7 @@
#include "arch/arm/fastmodel/CortexA76/cortex_a76.hh"
#include "arch/arm/fastmodel/iris/cpu.hh"
+#include "arch/arm/regs/misc.hh"
#include "base/logging.hh"
#include "dev/arm/base_gic.hh"
#include "sim/core.hh"
diff --git a/src/arch/arm/fastmodel/GIC/gic.cc
b/src/arch/arm/fastmodel/GIC/gic.cc
index 3133757..2830c83 100644
--- a/src/arch/arm/fastmodel/GIC/gic.cc
+++ b/src/arch/arm/fastmodel/GIC/gic.cc
@@ -70,7 +70,7 @@
SCGIC::SCGIC(const SCFastModelGICParams ¶ms,
sc_core::sc_module_name _name)
- : scx_evs_GIC(_name)
+ : scx_evs_GIC(_name), _params(params)
{
signalInterrupt.bind(signal_interrupt);
diff --git a/src/arch/arm/fastmodel/GIC/gic.hh
b/src/arch/arm/fastmodel/GIC/gic.hh
index 33997fd..b283108 100644
--- a/src/arch/arm/fastmodel/GIC/gic.hh
+++ b/src/arch/arm/fastmodel/GIC/gic.hh
@@ -81,6 +81,7 @@
};
std::unique_ptr<Terminator> terminator;
+ const SCFastModelGICParams &_params;
public:
SCGIC(const SCFastModelGICParams &p) : SCGIC(p, p.name.c_str()) {}
diff --git a/src/arch/arm/fastmodel/iris/isa.cc
b/src/arch/arm/fastmodel/iris/isa.cc
index 4aac71f..9312d4e 100644
--- a/src/arch/arm/fastmodel/iris/isa.cc
+++ b/src/arch/arm/fastmodel/iris/isa.cc
@@ -28,8 +28,8 @@
#include "arch/arm/fastmodel/iris/isa.hh"
#include "arch/arm/regs/misc.hh"
+#include "base/logging.hh"
#include "cpu/thread_context.hh"
-#include "params/IrisISA.hh"
#include "sim/serialize.hh"
void
@@ -40,3 +40,9 @@
miscRegs[i] = tc->readMiscRegNoEffect(i);
SERIALIZE_ARRAY(miscRegs, ArmISA::NUM_PHYS_MISCREGS);
}
+
+void
+Iris::ISA::copyRegsFrom(ThreadContext *src)
+{
+ panic("copyRegsFrom not implemented");
+}
diff --git a/src/arch/arm/fastmodel/iris/isa.hh
b/src/arch/arm/fastmodel/iris/isa.hh
index a7ae7b5..9b2828c 100644
--- a/src/arch/arm/fastmodel/iris/isa.hh
+++ b/src/arch/arm/fastmodel/iris/isa.hh
@@ -39,13 +39,15 @@
public:
ISA(const Params &p) : BaseISA(p) {}
- void serialize(CheckpointOut &cp) const;
+ void serialize(CheckpointOut &cp) const override;
+
+ void copyRegsFrom(ThreadContext *src) override;
bool
inUserMode() const override
{
- CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
- return ::inUserMode(cpsr);
+ ArmISA::CPSR cpsr = tc->readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
+ return ArmISA::inUserMode(cpsr);
}
};
diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc
b/src/arch/arm/fastmodel/iris/thread_context.cc
index 3116139..7bbc28b 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -672,7 +672,7 @@
call().resource_read(_instId, result, vecRegIds.at(idx));
size_t data_size = result.data.size() * (sizeof(*result.data.data()));
size_t size = std::min(data_size, reg.size());
- memcpy(reg.raw_ptr<void>(), (void *)result.data.data(), size);
+ memcpy(reg.as<uint8_t>(), (void *)result.data.data(), size);
return reg;
}
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh
b/src/arch/arm/fastmodel/iris/thread_context.hh
index d093138..76a2415 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -32,6 +32,7 @@
#include <map>
#include <memory>
+#include "arch/arm/regs/vec.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "iris/IrisInstance.h"
@@ -278,21 +279,22 @@
panic("%s not implemented.", __FUNCTION__);
}
- const VecRegContainer &readVecReg(const RegId ®) const override;
- VecRegContainer &
+ const ArmISA::VecRegContainer &readVecReg(const RegId ®) const
override;
+ ArmISA::VecRegContainer &
getWritableVecReg(const RegId ®) override
{
panic("%s not implemented.", __FUNCTION__);
}
- const VecElem &
+ const ArmISA::VecElem &
readVecElem(const RegId ®) const override
{
panic("%s not implemented.", __FUNCTION__);
}
- const VecPredRegContainer &readVecPredReg(const RegId ®) const
override;
- VecPredRegContainer &
+ const ArmISA::VecPredRegContainer &
+ readVecPredReg(const RegId ®) const override;
+ ArmISA::VecPredRegContainer &
getWritableVecPredReg(const RegId ®) override
{
panic("%s not implemented.", __FUNCTION__);
@@ -313,20 +315,20 @@
}
void
- setVecReg(const RegId ®, const VecRegContainer &val) override
+ setVecReg(const RegId ®, const ArmISA::VecRegContainer &val)
override
{
panic("%s not implemented.", __FUNCTION__);
}
void
- setVecElem(const RegId& reg, const VecElem& val) override
+ setVecElem(const RegId& reg, const ArmISA::VecElem& val) override
{
panic("%s not implemented.", __FUNCTION__);
}
void
setVecPredReg(const RegId ®,
- const VecPredRegContainer &val) override
+ const ArmISA::VecPredRegContainer &val) override
{
panic("%s not implemented.", __FUNCTION__);
}
@@ -412,38 +414,40 @@
panic("%s not implemented.", __FUNCTION__);
}
- const VecRegContainer &readVecRegFlat(RegIndex idx) const override;
- VecRegContainer &
+ const ArmISA::VecRegContainer &readVecRegFlat(RegIndex idx) const
override;
+ ArmISA::VecRegContainer &
getWritableVecRegFlat(RegIndex idx) override
{
panic("%s not implemented.", __FUNCTION__);
}
void
- setVecRegFlat(RegIndex idx, const VecRegContainer &val) override
+ setVecRegFlat(RegIndex idx, const ArmISA::VecRegContainer &val)
override
{
panic("%s not implemented.", __FUNCTION__);
}
- const VecElem&
+ const ArmISA::VecElem&
readVecElemFlat(RegIndex idx, const ElemIndex& elemIdx) const override
{
panic("%s not implemented.", __FUNCTION__);
}
void
setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx,
- const VecElem &val) override
+ const ArmISA::VecElem &val) override
{
panic("%s not implemented.", __FUNCTION__);
}
- const VecPredRegContainer &readVecPredRegFlat(RegIndex idx) const
override;
- VecPredRegContainer &
+ const ArmISA::VecPredRegContainer &
+ readVecPredRegFlat(RegIndex idx) const override;
+ ArmISA::VecPredRegContainer &
getWritableVecPredRegFlat(RegIndex idx) override
{
panic("%s not implemented.", __FUNCTION__);
}
void
- setVecPredRegFlat(RegIndex idx, const VecPredRegContainer &val)
override
+ setVecPredRegFlat(RegIndex idx,
+ const ArmISA::VecPredRegContainer &val) override
{
panic("%s not implemented.", __FUNCTION__);
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I457d32190aa65b0ecd2d6de3f4f5d42d922ae5d5
Gerrit-Change-Number: 46120
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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