Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46159 )
Change subject: mem-ruby,sim: Add support for VGA ROM memory region
......................................................................
mem-ruby,sim: Add support for VGA ROM memory region
Checks if the address is in a shadowed region, and sends the request
to pio to be serviced by the device backing up that range.
Based on: https://gem5-review.googlesource.com/c/amd/gem5/+/23484
Change-Id: I4d5b46cccd6203523008b2e9545d55eb62130964
---
M configs/example/gpufs/system/system.py
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/sim/System.py
M src/sim/system.cc
M src/sim/system.hh
6 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/configs/example/gpufs/system/system.py
b/configs/example/gpufs/system/system.py
index be4dd57..4ec3618 100644
--- a/configs/example/gpufs/system/system.py
+++ b/configs/example/gpufs/system/system.py
@@ -75,6 +75,9 @@
voltage_domain =
system.cpu_voltage_domain)
+ # Setup VGA ROM region
+ system.shadow_rom_ranges = [AddrRange(0xc0000, size = Addr('128kB'))]
+
# Create specified number of CPUs. GPUFS really only needs one.
system.cpu = [TestCPUClass(clk_domain=system.cpu_clk_domain, cpu_id=i)
for i in range(args.num_cpus)]
diff --git a/src/mem/ruby/system/RubyPort.cc
b/src/mem/ruby/system/RubyPort.cc
index 110ed3b..719530c 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -607,11 +607,26 @@
}
bool
+RubyPort::MemResponsePort::isShadowRomAddress(Addr addr) const
+{
+ bool is_shadowed = false;
+ RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
+ AddrRangeList ranges = ruby_port->system->getShadowRomRanges();
+
+ for (auto it = ranges.begin(); it != ranges.end(); ++it)
+ if (it->contains(addr))
+ is_shadowed = true;
+
+ return is_shadowed;
+}
+
+bool
RubyPort::MemResponsePort::isPhysMemAddress(PacketPtr pkt) const
{
RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
- return ruby_port->system->isMemAddr(pkt->getAddr())
- || ruby_port->system->isDeviceMemAddr(pkt);
+ Addr addr = pkt->getAddr();
+ return (ruby_port->system->isMemAddr(addr)
&& !isShadowRomAddress(addr))
+ || ruby_port->system->isDeviceMemAddr(pkt);
}
void
diff --git a/src/mem/ruby/system/RubyPort.hh
b/src/mem/ruby/system/RubyPort.hh
index 1d25ae9..e28dc6e 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -99,6 +99,7 @@
void addToRetryList();
private:
+ bool isShadowRomAddress(Addr addr) const;
bool isPhysMemAddress(PacketPtr pkt) const;
};
diff --git a/src/sim/System.py b/src/sim/System.py
index a2f6056..224a318 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -83,6 +83,10 @@
# I/O bridge or cache
mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main
memory")
+ # The ranges backed by a shadowed ROM
+ shadow_rom_ranges = VectorParam.AddrRange([], "Ranges backed by a " \
+ "shadowed ROM")
+
shared_backstore = Param.String("", "backstore's shmem segment
filename, "
"use to directly address the backstore from another host-OS
process. "
"Leave this empty to unset the MAP_SHARED flag.")
diff --git a/src/sim/system.cc b/src/sim/system.cc
index e2c42a9..90576eb 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -202,6 +202,8 @@
#endif
physmem(name() + ".physmem", p.memories, p.mmap_using_noreserve,
p.shared_backstore),
+ ShadowRomRanges(p.shadow_rom_ranges.begin(),
+ p.shadow_rom_ranges.end()),
memoryMode(p.mem_mode),
_cacheLineSize(p.cache_line_size),
numWorkIds(p.num_work_ids),
diff --git a/src/sim/system.hh b/src/sim/system.hh
index cbbd5e5..b22d441 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -378,6 +378,13 @@
*/
AbstractMemory *getDeviceMemory(RequestorID _id) const;
+ /*
+ * Return the list of address ranges backed by a shadowed ROM.
+ *
+ * @return List of address ranges backed by a shadowed ROM
+ */
+ AddrRangeList getShadowRomRanges() const { return ShadowRomRanges; }
+
/**
* Get the architecture.
*/
@@ -413,6 +420,8 @@
PhysicalMemory physmem;
+ AddrRangeList ShadowRomRanges;
+
Enums::MemoryMode memoryMode;
const unsigned int _cacheLineSize;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4d5b46cccd6203523008b2e9545d55eb62130964
Gerrit-Change-Number: 46159
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-MessageType: newchange
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