Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46323 )
Change subject: misc: Adopt the gem5 namespace
......................................................................
misc: Adopt the gem5 namespace
Apply the gem5 namespace to the codebase.
Some anonymous namespaces could theoretically be removed,
but since this change's main goal was to keep conflicts
at a minimum, it was decided not to modify much the
general shape of the files.
A few missing comments of the form "// namespace X" that
occurred before the newly added "} // namespace gem5"
have been added for consistency.
Change-Id: Ia53d404ec79c46edaa98f654e23bc3b0e179fe2d
Signed-off-by: Daniel R. Carvalho <oda...@yahoo.com.br>
---
M src/SConscript
M src/arch/amdgpu/gcn3/decoder.cc
M src/arch/amdgpu/gcn3/gpu_decoder.hh
M src/arch/amdgpu/gcn3/gpu_isa.hh
M src/arch/amdgpu/gcn3/gpu_mem_helpers.hh
M src/arch/amdgpu/gcn3/gpu_registers.hh
M src/arch/amdgpu/gcn3/gpu_types.hh
M src/arch/amdgpu/gcn3/insts/gpu_static_inst.cc
M src/arch/amdgpu/gcn3/insts/gpu_static_inst.hh
M src/arch/amdgpu/gcn3/insts/inst_util.hh
M src/arch/amdgpu/gcn3/insts/instructions.cc
M src/arch/amdgpu/gcn3/insts/instructions.hh
M src/arch/amdgpu/gcn3/insts/op_encodings.cc
M src/arch/amdgpu/gcn3/insts/op_encodings.hh
M src/arch/amdgpu/gcn3/isa.cc
M src/arch/amdgpu/gcn3/operand.hh
M src/arch/amdgpu/gcn3/registers.cc
M src/arch/amdgpu/vega/decoder.cc
M src/arch/amdgpu/vega/gpu_decoder.hh
M src/arch/amdgpu/vega/gpu_isa.hh
M src/arch/amdgpu/vega/gpu_mem_helpers.hh
M src/arch/amdgpu/vega/gpu_registers.hh
M src/arch/amdgpu/vega/gpu_types.hh
M src/arch/amdgpu/vega/insts/gpu_static_inst.cc
M src/arch/amdgpu/vega/insts/gpu_static_inst.hh
M src/arch/amdgpu/vega/insts/inst_util.hh
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
M src/arch/amdgpu/vega/insts/op_encodings.cc
M src/arch/amdgpu/vega/insts/op_encodings.hh
M src/arch/amdgpu/vega/isa.cc
M src/arch/amdgpu/vega/operand.hh
M src/arch/amdgpu/vega/registers.cc
M src/arch/arm/ArmFsWorkload.py
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmInterrupts.py
M src/arch/arm/ArmMMU.py
M src/arch/arm/ArmNativeTrace.py
M src/arch/arm/ArmPMU.py
M src/arch/arm/ArmSeWorkload.py
M src/arch/arm/ArmSemihosting.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/ArmTLB.py
M src/arch/arm/aapcs32.hh
M src/arch/arm/aapcs64.hh
M src/arch/arm/aapcs64.test.cc
M src/arch/arm/decoder.cc
M src/arch/arm/decoder.hh
M src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
M src/arch/arm/fastmodel/CortexA76/thread_context.hh
M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/CortexR52/thread_context.cc
M src/arch/arm/fastmodel/CortexR52/thread_context.hh
M src/arch/arm/fastmodel/FastModel.py
M src/arch/arm/fastmodel/GIC/FastModelGIC.py
M src/arch/arm/fastmodel/GIC/gic.cc
M src/arch/arm/fastmodel/GIC/gic.hh
M src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py
M src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
M src/arch/arm/fastmodel/PL330_DMAC/pl330.hh
M src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
M src/arch/arm/fastmodel/amba_ports.hh
M src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
M src/arch/arm/fastmodel/common/signal_receiver.hh
M src/arch/arm/fastmodel/fastmodel.cc
M src/arch/arm/fastmodel/iris/Iris.py
M src/arch/arm/fastmodel/iris/cpu.cc
M src/arch/arm/fastmodel/iris/cpu.hh
M src/arch/arm/fastmodel/iris/interrupts.cc
M src/arch/arm/fastmodel/iris/interrupts.hh
M src/arch/arm/fastmodel/iris/isa.cc
M src/arch/arm/fastmodel/iris/isa.hh
M src/arch/arm/fastmodel/iris/memory_spaces.hh
M src/arch/arm/fastmodel/iris/mmu.hh
M src/arch/arm/fastmodel/iris/thread_context.cc
M src/arch/arm/fastmodel/iris/thread_context.hh
M src/arch/arm/fastmodel/iris/tlb.cc
M src/arch/arm/fastmodel/iris/tlb.hh
M src/arch/arm/fastmodel/protocol/exported_clock_rate_control.hh
M src/arch/arm/fastmodel/protocol/signal_interrupt.hh
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/freebsd/freebsd.cc
M src/arch/arm/freebsd/freebsd.hh
M src/arch/arm/freebsd/fs_workload.cc
M src/arch/arm/freebsd/fs_workload.hh
M src/arch/arm/freebsd/se_workload.cc
M src/arch/arm/freebsd/se_workload.hh
M src/arch/arm/fs_workload.cc
M src/arch/arm/fs_workload.hh
M src/arch/arm/htm.cc
M src/arch/arm/htm.hh
M src/arch/arm/insts/branch.cc
M src/arch/arm/insts/branch.hh
M src/arch/arm/insts/branch64.cc
M src/arch/arm/insts/branch64.hh
M src/arch/arm/insts/crypto.cc
M src/arch/arm/insts/crypto.hh
M src/arch/arm/insts/data64.cc
M src/arch/arm/insts/data64.hh
M src/arch/arm/insts/fplib.cc
M src/arch/arm/insts/fplib.hh
M src/arch/arm/insts/macromem.cc
M src/arch/arm/insts/macromem.hh
M src/arch/arm/insts/mem.cc
M src/arch/arm/insts/mem.hh
M src/arch/arm/insts/mem64.cc
M src/arch/arm/insts/mem64.hh
M src/arch/arm/insts/misc.cc
M src/arch/arm/insts/misc.hh
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/misc64.hh
M src/arch/arm/insts/mult.hh
M src/arch/arm/insts/neon64_mem.hh
M src/arch/arm/insts/pred_inst.cc
M src/arch/arm/insts/pred_inst.hh
M src/arch/arm/insts/pseudo.cc
M src/arch/arm/insts/pseudo.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
M src/arch/arm/insts/sve.cc
M src/arch/arm/insts/sve.hh
M src/arch/arm/insts/sve_macromem.hh
M src/arch/arm/insts/sve_mem.cc
M src/arch/arm/insts/sve_mem.hh
M src/arch/arm/insts/tme64.cc
M src/arch/arm/insts/tme64.hh
M src/arch/arm/insts/tme64classic.cc
M src/arch/arm/insts/tme64ruby.cc
M src/arch/arm/insts/vfp.cc
M src/arch/arm/insts/vfp.hh
M src/arch/arm/interrupts.cc
M src/arch/arm/interrupts.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa_device.cc
M src/arch/arm/isa_device.hh
M src/arch/arm/kvm/ArmKvmCPU.py
M src/arch/arm/kvm/ArmV8KvmCPU.py
M src/arch/arm/kvm/BaseArmKvmCPU.py
M src/arch/arm/kvm/KvmGic.py
M src/arch/arm/kvm/arm_cpu.cc
M src/arch/arm/kvm/arm_cpu.hh
M src/arch/arm/kvm/armv8_cpu.cc
M src/arch/arm/kvm/armv8_cpu.hh
M src/arch/arm/kvm/base_cpu.cc
M src/arch/arm/kvm/base_cpu.hh
M src/arch/arm/kvm/gic.cc
M src/arch/arm/kvm/gic.hh
M src/arch/arm/linux/atag.hh
M src/arch/arm/linux/fs_workload.cc
M src/arch/arm/linux/fs_workload.hh
M src/arch/arm/linux/linux.hh
M src/arch/arm/linux/process.cc
M src/arch/arm/linux/process.hh
M src/arch/arm/linux/se_workload.cc
M src/arch/arm/linux/se_workload.hh
M src/arch/arm/locked_mem.hh
M src/arch/arm/mmu.cc
M src/arch/arm/mmu.hh
M src/arch/arm/nativetrace.cc
M src/arch/arm/nativetrace.hh
M src/arch/arm/page_size.hh
M src/arch/arm/pagetable.hh
M src/arch/arm/pauth_helpers.cc
M src/arch/arm/pauth_helpers.hh
M src/arch/arm/pcstate.hh
M src/arch/arm/pmu.cc
M src/arch/arm/pmu.hh
M src/arch/arm/process.cc
M src/arch/arm/process.hh
M src/arch/arm/qarma.cc
M src/arch/arm/qarma.hh
M src/arch/arm/reg_abi.cc
M src/arch/arm/reg_abi.hh
M src/arch/arm/regs/cc.hh
M src/arch/arm/regs/int.hh
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
M src/arch/arm/regs/misc_types.hh
M src/arch/arm/regs/vec.hh
M src/arch/arm/remote_gdb.cc
M src/arch/arm/remote_gdb.hh
M src/arch/arm/se_workload.hh
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/semihosting.cc
M src/arch/arm/semihosting.hh
M src/arch/arm/stacktrace.hh
M src/arch/arm/stage2_lookup.cc
M src/arch/arm/stage2_lookup.hh
M src/arch/arm/stage2_mmu.cc
M src/arch/arm/stage2_mmu.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/arm/tlbi_op.cc
M src/arch/arm/tlbi_op.hh
M src/arch/arm/tracers/TarmacTrace.py
M src/arch/arm/tracers/tarmac_base.cc
M src/arch/arm/tracers/tarmac_base.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/tracers/tarmac_parser.hh
M src/arch/arm/tracers/tarmac_record.cc
M src/arch/arm/tracers/tarmac_record.hh
M src/arch/arm/tracers/tarmac_record_v8.cc
M src/arch/arm/tracers/tarmac_record_v8.hh
M src/arch/arm/tracers/tarmac_tracer.cc
M src/arch/arm/tracers/tarmac_tracer.hh
M src/arch/arm/types.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/arch/gcn3/registers.hh
M src/arch/generic/BaseISA.py
M src/arch/generic/BaseInterrupts.py
M src/arch/generic/BaseMMU.py
M src/arch/generic/BaseTLB.py
M src/arch/generic/debugfaults.hh
M src/arch/generic/decode_cache.hh
M src/arch/generic/decoder.cc
M src/arch/generic/decoder.hh
M src/arch/generic/freebsd/threadinfo.hh
M src/arch/generic/htm.cc
M src/arch/generic/htm.hh
M src/arch/generic/interrupts.hh
M src/arch/generic/isa.hh
M src/arch/generic/linux/threadinfo.hh
M src/arch/generic/locked_mem.hh
M src/arch/generic/memhelpers.hh
M src/arch/generic/mmu.cc
M src/arch/generic/mmu.hh
M src/arch/generic/tlb.hh
M src/arch/generic/types.hh
M src/arch/generic/vec_pred_reg.hh
M src/arch/generic/vec_reg.hh
M src/arch/mips/MipsISA.py
M src/arch/mips/MipsInterrupts.py
M src/arch/mips/MipsMMU.py
M src/arch/mips/MipsSeWorkload.py
M src/arch/mips/MipsTLB.py
M src/arch/mips/decoder.cc
M src/arch/mips/decoder.hh
M src/arch/mips/dsp.cc
M src/arch/mips/dsp.hh
M src/arch/mips/dt_constants.hh
M src/arch/mips/faults.cc
M src/arch/mips/faults.hh
M src/arch/mips/idle_event.cc
M src/arch/mips/idle_event.hh
M src/arch/mips/interrupts.cc
M src/arch/mips/interrupts.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/mips/linux/aligned.hh
M src/arch/mips/linux/hwrpb.hh
M src/arch/mips/linux/linux.hh
M src/arch/mips/linux/se_workload.cc
M src/arch/mips/linux/se_workload.hh
M src/arch/mips/linux/thread_info.hh
M src/arch/mips/locked_mem.hh
M src/arch/mips/mmu.hh
M src/arch/mips/mt.hh
M src/arch/mips/mt_constants.hh
M src/arch/mips/page_size.hh
M src/arch/mips/pagetable.cc
M src/arch/mips/pagetable.hh
M src/arch/mips/pra_constants.hh
M src/arch/mips/process.cc
M src/arch/mips/process.hh
M src/arch/mips/regs/float.hh
M src/arch/mips/regs/int.hh
M src/arch/mips/regs/misc.hh
M src/arch/mips/remote_gdb.cc
M src/arch/mips/remote_gdb.hh
M src/arch/mips/se_workload.cc
M src/arch/mips/se_workload.hh
M src/arch/mips/stacktrace.hh
M src/arch/mips/tlb.cc
M src/arch/mips/tlb.hh
M src/arch/mips/types.hh
M src/arch/mips/utility.cc
M src/arch/mips/utility.hh
M src/arch/mips/vecregs.hh
M src/arch/null/locked_mem.hh
M src/arch/null/page_size.hh
M src/arch/null/pcstate.hh
M src/arch/null/remote_gdb.hh
M src/arch/null/utility.hh
M src/arch/null/vecregs.hh
M src/arch/power/PowerISA.py
M src/arch/power/PowerInterrupts.py
M src/arch/power/PowerMMU.py
M src/arch/power/PowerSeWorkload.py
M src/arch/power/PowerTLB.py
M src/arch/power/decoder.cc
M src/arch/power/decoder.hh
M src/arch/power/faults.hh
M src/arch/power/insts/branch.cc
M src/arch/power/insts/branch.hh
M src/arch/power/insts/condition.cc
M src/arch/power/insts/condition.hh
M src/arch/power/insts/floating.cc
M src/arch/power/insts/floating.hh
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
M src/arch/power/insts/mem.cc
M src/arch/power/insts/mem.hh
M src/arch/power/insts/misc.cc
M src/arch/power/insts/misc.hh
M src/arch/power/insts/static_inst.cc
M src/arch/power/insts/static_inst.hh
M src/arch/power/interrupts.hh
M src/arch/power/isa.cc
M src/arch/power/isa.hh
M src/arch/power/linux/linux.hh
M src/arch/power/linux/se_workload.cc
M src/arch/power/linux/se_workload.hh
M src/arch/power/locked_mem.hh
M src/arch/power/mmu.hh
M src/arch/power/page_size.hh
M src/arch/power/pagetable.cc
M src/arch/power/pagetable.hh
M src/arch/power/process.hh
M src/arch/power/regs/float.hh
M src/arch/power/regs/int.hh
M src/arch/power/regs/misc.hh
M src/arch/power/remote_gdb.cc
M src/arch/power/remote_gdb.hh
M src/arch/power/se_workload.cc
M src/arch/power/se_workload.hh
M src/arch/power/stacktrace.hh
M src/arch/power/tlb.cc
M src/arch/power/tlb.hh
M src/arch/power/types.hh
M src/arch/power/vecregs.hh
M src/arch/riscv/PMAChecker.py
M src/arch/riscv/PMP.py
M src/arch/riscv/RiscvFsWorkload.py
M src/arch/riscv/RiscvISA.py
M src/arch/riscv/RiscvInterrupts.py
M src/arch/riscv/RiscvMMU.py
M src/arch/riscv/RiscvSeWorkload.py
M src/arch/riscv/RiscvTLB.py
M src/arch/riscv/bare_metal/fs_workload.cc
M src/arch/riscv/bare_metal/fs_workload.hh
M src/arch/riscv/decoder.cc
M src/arch/riscv/decoder.hh
M src/arch/riscv/faults.cc
M src/arch/riscv/faults.hh
M src/arch/riscv/idle_event.cc
M src/arch/riscv/idle_event.hh
M src/arch/riscv/insts/amo.cc
M src/arch/riscv/insts/amo.hh
M src/arch/riscv/insts/compressed.cc
M src/arch/riscv/insts/compressed.hh
M src/arch/riscv/insts/mem.cc
M src/arch/riscv/insts/mem.hh
M src/arch/riscv/insts/pseudo.hh
M src/arch/riscv/insts/standard.cc
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/insts/static_inst.cc
M src/arch/riscv/insts/static_inst.hh
M src/arch/riscv/insts/unknown.hh
M src/arch/riscv/interrupts.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/linux/fs_workload.cc
M src/arch/riscv/linux/fs_workload.hh
M src/arch/riscv/linux/linux.hh
M src/arch/riscv/linux/se_workload.cc
M src/arch/riscv/linux/se_workload.hh
M src/arch/riscv/locked_mem.cc
M src/arch/riscv/locked_mem.hh
M src/arch/riscv/mmu.hh
M src/arch/riscv/page_size.hh
M src/arch/riscv/pagetable.cc
M src/arch/riscv/pagetable.hh
M src/arch/riscv/pagetable_walker.cc
M src/arch/riscv/pagetable_walker.hh
M src/arch/riscv/pcstate.hh
M src/arch/riscv/pma_checker.cc
M src/arch/riscv/pma_checker.hh
M src/arch/riscv/pmp.cc
M src/arch/riscv/pmp.hh
M src/arch/riscv/pra_constants.hh
M src/arch/riscv/process.cc
M src/arch/riscv/process.hh
M src/arch/riscv/reg_abi.cc
M src/arch/riscv/reg_abi.hh
M src/arch/riscv/regs/float.hh
M src/arch/riscv/regs/int.hh
M src/arch/riscv/regs/misc.hh
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
M src/arch/riscv/se_workload.hh
M src/arch/riscv/stacktrace.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
M src/arch/riscv/types.hh
M src/arch/riscv/utility.hh
M src/arch/riscv/vecregs.hh
M src/arch/sparc/SparcFsWorkload.py
M src/arch/sparc/SparcISA.py
M src/arch/sparc/SparcInterrupts.py
M src/arch/sparc/SparcMMU.py
M src/arch/sparc/SparcNativeTrace.py
M src/arch/sparc/SparcSeWorkload.py
M src/arch/sparc/SparcTLB.py
M src/arch/sparc/asi.cc
M src/arch/sparc/asi.hh
M src/arch/sparc/decoder.cc
M src/arch/sparc/decoder.hh
M src/arch/sparc/faults.cc
M src/arch/sparc/faults.hh
M src/arch/sparc/fs_workload.cc
M src/arch/sparc/fs_workload.hh
M src/arch/sparc/handlers.hh
M src/arch/sparc/insts/blockmem.cc
M src/arch/sparc/insts/blockmem.hh
M src/arch/sparc/insts/branch.cc
M src/arch/sparc/insts/branch.hh
M src/arch/sparc/insts/integer.cc
M src/arch/sparc/insts/integer.hh
M src/arch/sparc/insts/mem.cc
M src/arch/sparc/insts/mem.hh
M src/arch/sparc/insts/micro.cc
M src/arch/sparc/insts/micro.hh
M src/arch/sparc/insts/nop.hh
M src/arch/sparc/insts/priv.cc
M src/arch/sparc/insts/priv.hh
M src/arch/sparc/insts/static_inst.cc
M src/arch/sparc/insts/static_inst.hh
M src/arch/sparc/insts/trap.cc
M src/arch/sparc/insts/trap.hh
M src/arch/sparc/insts/unimp.hh
M src/arch/sparc/insts/unknown.hh
M src/arch/sparc/interrupts.hh
M src/arch/sparc/isa.cc
M src/arch/sparc/isa.hh
M src/arch/sparc/linux/linux.hh
M src/arch/sparc/linux/se_workload.cc
M src/arch/sparc/linux/se_workload.hh
M src/arch/sparc/linux/syscalls.cc
M src/arch/sparc/locked_mem.hh
M src/arch/sparc/mmu.hh
M src/arch/sparc/nativetrace.cc
M src/arch/sparc/nativetrace.hh
M src/arch/sparc/page_size.hh
M src/arch/sparc/pagetable.cc
M src/arch/sparc/pagetable.hh
M src/arch/sparc/process.cc
M src/arch/sparc/process.hh
M src/arch/sparc/pseudo_inst_abi.hh
M src/arch/sparc/regs/float.hh
M src/arch/sparc/regs/int.hh
M src/arch/sparc/regs/misc.hh
M src/arch/sparc/remote_gdb.cc
M src/arch/sparc/remote_gdb.hh
M src/arch/sparc/se_workload.cc
M src/arch/sparc/se_workload.hh
M src/arch/sparc/solaris/solaris.cc
M src/arch/sparc/solaris/solaris.hh
M src/arch/sparc/sparc_traits.hh
M src/arch/sparc/stacktrace.hh
M src/arch/sparc/tlb.cc
M src/arch/sparc/tlb.hh
M src/arch/sparc/tlb_map.hh
M src/arch/sparc/types.hh
M src/arch/sparc/ua2005.cc
M src/arch/sparc/vecregs.hh
M src/arch/x86/X86FsWorkload.py
M src/arch/x86/X86ISA.py
M src/arch/x86/X86LocalApic.py
M src/arch/x86/X86MMU.py
M src/arch/x86/X86NativeTrace.py
M src/arch/x86/X86SeWorkload.py
M src/arch/x86/X86TLB.py
M src/arch/x86/bios/ACPI.py
M src/arch/x86/bios/E820.py
M src/arch/x86/bios/IntelMP.py
M src/arch/x86/bios/SMBios.py
M src/arch/x86/bios/acpi.cc
M src/arch/x86/bios/acpi.hh
M src/arch/x86/bios/e820.cc
M src/arch/x86/bios/e820.hh
M src/arch/x86/bios/intelmp.cc
M src/arch/x86/bios/intelmp.hh
M src/arch/x86/bios/smbios.cc
M src/arch/x86/bios/smbios.hh
M src/arch/x86/cpuid.cc
M src/arch/x86/cpuid.hh
M src/arch/x86/decoder.cc
M src/arch/x86/decoder.hh
M src/arch/x86/decoder_tables.cc
M src/arch/x86/emulenv.cc
M src/arch/x86/emulenv.hh
M src/arch/x86/faults.cc
M src/arch/x86/faults.hh
M src/arch/x86/fs_workload.cc
M src/arch/x86/fs_workload.hh
M src/arch/x86/insts/badmicroop.cc
M src/arch/x86/insts/badmicroop.hh
M src/arch/x86/insts/macroop.hh
M src/arch/x86/insts/microdebug.hh
M src/arch/x86/insts/microfpop.hh
M src/arch/x86/insts/microldstop.hh
M src/arch/x86/insts/micromediaop.hh
M src/arch/x86/insts/microop.cc
M src/arch/x86/insts/microop.hh
M src/arch/x86/insts/microop_args.hh
M src/arch/x86/insts/microregop.cc
M src/arch/x86/insts/microregop.hh
M src/arch/x86/insts/microspecop.hh
M src/arch/x86/insts/static_inst.cc
M src/arch/x86/insts/static_inst.hh
M src/arch/x86/interrupts.cc
M src/arch/x86/interrupts.hh
M src/arch/x86/intmessage.hh
M src/arch/x86/isa.cc
M src/arch/x86/isa.hh
M src/arch/x86/ldstflags.hh
M src/arch/x86/linux/fs_workload.cc
M src/arch/x86/linux/fs_workload.hh
M src/arch/x86/linux/linux.hh
M src/arch/x86/linux/se_workload.cc
M src/arch/x86/linux/se_workload.hh
M src/arch/x86/linux/syscall_tbl32.cc
M src/arch/x86/linux/syscall_tbl64.cc
M src/arch/x86/linux/syscalls.cc
M src/arch/x86/linux/syscalls.hh
M src/arch/x86/locked_mem.hh
M src/arch/x86/memhelpers.hh
M src/arch/x86/microcode_rom.hh
M src/arch/x86/mmu.hh
M src/arch/x86/nativetrace.cc
M src/arch/x86/nativetrace.hh
M src/arch/x86/page_size.hh
M src/arch/x86/pagetable.cc
M src/arch/x86/pagetable.hh
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/pagetable_walker.hh
M src/arch/x86/pcstate.hh
M src/arch/x86/process.cc
M src/arch/x86/process.hh
M src/arch/x86/pseudo_inst_abi.hh
M src/arch/x86/regs/apic.hh
M src/arch/x86/regs/ccr.hh
M src/arch/x86/regs/float.hh
M src/arch/x86/regs/int.hh
M src/arch/x86/regs/misc.hh
M src/arch/x86/regs/msr.cc
M src/arch/x86/regs/msr.hh
M src/arch/x86/regs/segment.hh
M src/arch/x86/remote_gdb.cc
M src/arch/x86/remote_gdb.hh
M src/arch/x86/se_workload.hh
M src/arch/x86/stacktrace.hh
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
M src/arch/x86/types.cc
M src/arch/x86/types.hh
M src/arch/x86/utility.cc
M src/arch/x86/utility.hh
M src/arch/x86/vecregs.hh
M src/arch/x86/x86_traits.hh
M src/base/addr_range.hh
M src/base/addr_range.test.cc
M src/base/addr_range_map.hh
M src/base/addr_range_map.test.cc
M src/base/amo.hh
M src/base/amo.test.cc
M src/base/atomicio.cc
M src/base/atomicio.hh
M src/base/atomicio.test.cc
M src/base/barrier.hh
M src/base/bitfield.cc
M src/base/bitfield.hh
M src/base/bitfield.test.cc
M src/base/bitunion.hh
M src/base/bitunion.test.cc
M src/base/bmpwriter.cc
M src/base/bmpwriter.hh
M src/base/callback.hh
M src/base/cast.hh
M src/base/channel_addr.cc
M src/base/channel_addr.hh
M src/base/channel_addr.test.cc
M src/base/chunk_generator.hh
M src/base/chunk_generator.test.cc
M src/base/circlebuf.hh
M src/base/circlebuf.test.cc
M src/base/circular_queue.hh
M src/base/circular_queue.test.cc
M src/base/condcodes.hh
M src/base/condcodes.test.cc
M src/base/cprintf.cc
M src/base/cprintf.hh
M src/base/cprintf.test.cc
M src/base/cprintf_formats.hh
M src/base/cprintftime.cc
M src/base/crc.hh
M src/base/date.cc
M src/base/debug.cc
M src/base/debug.hh
M src/base/debug.test.cc
M src/base/fiber.cc
M src/base/fiber.hh
M src/base/fiber.test.cc
M src/base/filters/BloomFilters.py
M src/base/filters/base.hh
M src/base/filters/block_bloom_filter.cc
M src/base/filters/block_bloom_filter.hh
M src/base/filters/bulk_bloom_filter.cc
M src/base/filters/bulk_bloom_filter.hh
M src/base/filters/h3_bloom_filter.cc
M src/base/filters/h3_bloom_filter.hh
M src/base/filters/multi_bit_sel_bloom_filter.cc
M src/base/filters/multi_bit_sel_bloom_filter.hh
M src/base/filters/multi_bloom_filter.cc
M src/base/filters/multi_bloom_filter.hh
M src/base/filters/perfect_bloom_filter.cc
M src/base/filters/perfect_bloom_filter.hh
M src/base/flags.hh
M src/base/flags.test.cc
M src/base/framebuffer.cc
M src/base/framebuffer.hh
M src/base/gtest/cur_tick_fake.hh
M src/base/gtest/logging.cc
M src/base/gtest/logging.hh
M src/base/gtest/logging_mock.cc
M src/base/hostinfo.cc
M src/base/hostinfo.hh
M src/base/imgwriter.cc
M src/base/imgwriter.hh
M src/base/inet.cc
M src/base/inet.hh
M src/base/inifile.cc
M src/base/inifile.hh
M src/base/inifile.test.cc
M src/base/intmath.hh
M src/base/intmath.test.cc
M src/base/loader/dtb_file.cc
M src/base/loader/dtb_file.hh
M src/base/loader/elf_object.cc
M src/base/loader/elf_object.hh
M src/base/loader/image_file.hh
M src/base/loader/image_file_data.cc
M src/base/loader/image_file_data.hh
M src/base/loader/image_file_data.test.cc
M src/base/loader/memory_image.cc
M src/base/loader/memory_image.hh
M src/base/loader/object_file.cc
M src/base/loader/object_file.hh
M src/base/loader/raw_image.hh
M src/base/loader/small_image_file.test.hh
M src/base/loader/symtab.cc
M src/base/loader/symtab.hh
M src/base/logging.cc
M src/base/logging.hh
M src/base/logging.test.cc
M src/base/match.cc
M src/base/match.hh
M src/base/match.test.cc
M src/base/named.hh
M src/base/named.test.cc
M src/base/output.cc
M src/base/output.hh
M src/base/pixel.cc
M src/base/pixel.hh
M src/base/pixel.test.cc
M src/base/pngwriter.cc
M src/base/pngwriter.hh
M src/base/pollevent.cc
M src/base/pollevent.hh
M src/base/printable.hh
M src/base/random.cc
M src/base/random.hh
M src/base/refcnt.hh
M src/base/refcnt.test.cc
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
M src/base/sat_counter.hh
M src/base/sat_counter.test.cc
M src/base/socket.cc
M src/base/socket.hh
M src/base/socket.test.cc
M src/base/statistics.cc
M src/base/statistics.hh
M src/base/stats/group.cc
M src/base/stats/group.hh
M src/base/stats/hdf5.cc
M src/base/stats/hdf5.hh
M src/base/stats/info.cc
M src/base/stats/info.hh
M src/base/stats/output.hh
M src/base/stats/storage.cc
M src/base/stats/storage.hh
M src/base/stats/storage.test.cc
M src/base/stats/text.cc
M src/base/stats/text.hh
M src/base/stats/types.hh
M src/base/stats/units.hh
M src/base/stats/units.test.cc
M src/base/stl_helpers.hh
M src/base/str.cc
M src/base/str.hh
M src/base/str.test.cc
M src/base/temperature.cc
M src/base/temperature.hh
M src/base/temperature.test.cc
M src/base/time.cc
M src/base/time.hh
M src/base/trace.cc
M src/base/trace.hh
M src/base/trie.hh
M src/base/trie.test.cc
M src/base/types.cc
M src/base/types.hh
M src/base/types.test.cc
M src/base/uncontended_mutex.hh
M src/base/uncontended_mutex.test.cc
M src/base/version.cc
M src/base/vnc/Vnc.py
M src/base/vnc/vncinput.cc
M src/base/vnc/vncinput.hh
M src/base/vnc/vncserver.cc
M src/base/vnc/vncserver.hh
M src/cpu/BaseCPU.py
M src/cpu/CPUTracers.py
M src/cpu/CheckerCPU.py
M src/cpu/DummyChecker.py
M src/cpu/FuncUnit.py
M src/cpu/InstPBTrace.py
M src/cpu/TimingExpr.py
M src/cpu/activity.cc
M src/cpu/activity.hh
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/checker/cpu_impl.hh
M src/cpu/checker/thread_context.hh
M src/cpu/decode_cache.hh
M src/cpu/dummy_checker.hh
M src/cpu/exec_context.hh
M src/cpu/exetrace.cc
M src/cpu/exetrace.hh
M src/cpu/func_unit.cc
M src/cpu/func_unit.hh
M src/cpu/inst_pb_trace.cc
M src/cpu/inst_pb_trace.hh
M src/cpu/inst_res.hh
M src/cpu/inst_seq.hh
M src/cpu/inteltrace.cc
M src/cpu/inteltrace.hh
M src/cpu/kvm/BaseKvmCPU.py
M src/cpu/kvm/KvmVM.py
M src/cpu/kvm/X86KvmCPU.py
M src/cpu/kvm/base.cc
M src/cpu/kvm/base.hh
M src/cpu/kvm/device.cc
M src/cpu/kvm/device.hh
M src/cpu/kvm/perfevent.cc
M src/cpu/kvm/perfevent.hh
M src/cpu/kvm/timer.cc
M src/cpu/kvm/timer.hh
M src/cpu/kvm/vm.cc
M src/cpu/kvm/vm.hh
M src/cpu/kvm/x86_cpu.cc
M src/cpu/kvm/x86_cpu.hh
M src/cpu/minor/MinorCPU.py
M src/cpu/minor/activity.cc
M src/cpu/minor/activity.hh
M src/cpu/minor/buffers.hh
M src/cpu/minor/cpu.cc
M src/cpu/minor/cpu.hh
M src/cpu/minor/decode.cc
M src/cpu/minor/decode.hh
M src/cpu/minor/dyn_inst.cc
M src/cpu/minor/dyn_inst.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/execute.cc
M src/cpu/minor/execute.hh
M src/cpu/minor/fetch1.cc
M src/cpu/minor/fetch1.hh
M src/cpu/minor/fetch2.cc
M src/cpu/minor/fetch2.hh
M src/cpu/minor/func_unit.cc
M src/cpu/minor/func_unit.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/minor/pipe_data.cc
M src/cpu/minor/pipe_data.hh
M src/cpu/minor/pipeline.cc
M src/cpu/minor/pipeline.hh
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/minor/stats.cc
M src/cpu/minor/stats.hh
M src/cpu/minor/trace.hh
M src/cpu/nativetrace.cc
M src/cpu/nativetrace.hh
M src/cpu/nop_static_inst.cc
M src/cpu/nop_static_inst.hh
M src/cpu/null_static_inst.cc
M src/cpu/null_static_inst.hh
M src/cpu/o3/FUPool.py
M src/cpu/o3/O3CPU.py
M src/cpu/o3/O3Checker.py
M src/cpu/o3/checker.cc
M src/cpu/o3/checker.hh
M src/cpu/o3/comm.hh
M src/cpu/o3/commit.cc
M src/cpu/o3/commit.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/decode.cc
M src/cpu/o3/decode.hh
M src/cpu/o3/dep_graph.hh
M src/cpu/o3/dyn_inst.cc
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/dyn_inst_ptr.hh
M src/cpu/o3/fetch.cc
M src/cpu/o3/fetch.hh
M src/cpu/o3/free_list.cc
M src/cpu/o3/free_list.hh
M src/cpu/o3/fu_pool.cc
M src/cpu/o3/fu_pool.hh
M src/cpu/o3/iew.cc
M src/cpu/o3/iew.hh
M src/cpu/o3/inst_queue.cc
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/limits.hh
M src/cpu/o3/lsq.cc
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_unit.cc
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/mem_dep_unit.cc
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/probe/ElasticTrace.py
M src/cpu/o3/probe/SimpleTrace.py
M src/cpu/o3/probe/elastic_trace.cc
M src/cpu/o3/probe/elastic_trace.hh
M src/cpu/o3/probe/simple_trace.cc
M src/cpu/o3/probe/simple_trace.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename.cc
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/o3/rob.cc
M src/cpu/o3/rob.hh
M src/cpu/o3/scoreboard.cc
M src/cpu/o3/scoreboard.hh
M src/cpu/o3/store_set.cc
M src/cpu/o3/store_set.hh
M src/cpu/o3/thread_context.cc
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_state.cc
M src/cpu/o3/thread_state.hh
M src/cpu/op_class.hh
M src/cpu/pc_event.cc
M src/cpu/pc_event.hh
M src/cpu/pred/2bit_local.cc
M src/cpu/pred/2bit_local.hh
M src/cpu/pred/BranchPredictor.py
M src/cpu/pred/bi_mode.cc
M src/cpu/pred/bi_mode.hh
M src/cpu/pred/bpred_unit.cc
M src/cpu/pred/bpred_unit.hh
M src/cpu/pred/btb.cc
M src/cpu/pred/btb.hh
M src/cpu/pred/indirect.hh
M src/cpu/pred/loop_predictor.cc
M src/cpu/pred/loop_predictor.hh
M src/cpu/pred/ltage.cc
M src/cpu/pred/ltage.hh
M src/cpu/pred/multiperspective_perceptron.cc
M src/cpu/pred/multiperspective_perceptron.hh
M src/cpu/pred/multiperspective_perceptron_64KB.cc
M src/cpu/pred/multiperspective_perceptron_64KB.hh
M src/cpu/pred/multiperspective_perceptron_8KB.cc
M src/cpu/pred/multiperspective_perceptron_8KB.hh
M src/cpu/pred/multiperspective_perceptron_tage.cc
M src/cpu/pred/multiperspective_perceptron_tage.hh
M src/cpu/pred/multiperspective_perceptron_tage_64KB.cc
M src/cpu/pred/multiperspective_perceptron_tage_64KB.hh
M src/cpu/pred/multiperspective_perceptron_tage_8KB.cc
M src/cpu/pred/multiperspective_perceptron_tage_8KB.hh
M src/cpu/pred/ras.cc
M src/cpu/pred/ras.hh
M src/cpu/pred/simple_indirect.cc
M src/cpu/pred/simple_indirect.hh
M src/cpu/pred/statistical_corrector.cc
M src/cpu/pred/statistical_corrector.hh
M src/cpu/pred/tage.cc
M src/cpu/pred/tage.hh
M src/cpu/pred/tage_base.cc
M src/cpu/pred/tage_base.hh
M src/cpu/pred/tage_sc_l.cc
M src/cpu/pred/tage_sc_l.hh
M src/cpu/pred/tage_sc_l_64KB.cc
M src/cpu/pred/tage_sc_l_64KB.hh
M src/cpu/pred/tage_sc_l_8KB.cc
M src/cpu/pred/tage_sc_l_8KB.hh
M src/cpu/pred/tournament.cc
M src/cpu/pred/tournament.hh
M src/cpu/profile.cc
M src/cpu/profile.hh
M src/cpu/reg_class.cc
M src/cpu/reg_class.hh
M src/cpu/simple/AtomicSimpleCPU.py
M src/cpu/simple/BaseSimpleCPU.py
M src/cpu/simple/NonCachingSimpleCPU.py
M src/cpu/simple/TimingSimpleCPU.py
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.cc
M src/cpu/simple/base.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple/noncaching.cc
M src/cpu/simple/noncaching.hh
M src/cpu/simple/probes/SimPoint.py
M src/cpu/simple/probes/simpoint.cc
M src/cpu/simple/probes/simpoint.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/smt.hh
M src/cpu/static_inst.cc
M src/cpu/static_inst.hh
M src/cpu/static_inst_fwd.hh
M src/cpu/testers/directedtest/DirectedGenerator.cc
M src/cpu/testers/directedtest/DirectedGenerator.hh
M src/cpu/testers/directedtest/InvalidateGenerator.cc
M src/cpu/testers/directedtest/InvalidateGenerator.hh
M src/cpu/testers/directedtest/RubyDirectedTester.cc
M src/cpu/testers/directedtest/RubyDirectedTester.hh
M src/cpu/testers/directedtest/RubyDirectedTester.py
M src/cpu/testers/directedtest/SeriesRequestGenerator.cc
M src/cpu/testers/directedtest/SeriesRequestGenerator.hh
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
M src/cpu/testers/gpu_ruby_test/CpuThread.py
M src/cpu/testers/gpu_ruby_test/DmaThread.py
M src/cpu/testers/gpu_ruby_test/GpuWavefront.py
M src/cpu/testers/gpu_ruby_test/ProtocolTester.py
M src/cpu/testers/gpu_ruby_test/TesterDma.py
M src/cpu/testers/gpu_ruby_test/TesterThread.py
M src/cpu/testers/gpu_ruby_test/address_manager.cc
M src/cpu/testers/gpu_ruby_test/address_manager.hh
M src/cpu/testers/gpu_ruby_test/cpu_thread.cc
M src/cpu/testers/gpu_ruby_test/cpu_thread.hh
M src/cpu/testers/gpu_ruby_test/dma_thread.cc
M src/cpu/testers/gpu_ruby_test/dma_thread.hh
M src/cpu/testers/gpu_ruby_test/episode.cc
M src/cpu/testers/gpu_ruby_test/episode.hh
M src/cpu/testers/gpu_ruby_test/gpu_wavefront.cc
M src/cpu/testers/gpu_ruby_test/gpu_wavefront.hh
M src/cpu/testers/gpu_ruby_test/protocol_tester.cc
M src/cpu/testers/gpu_ruby_test/protocol_tester.hh
M src/cpu/testers/gpu_ruby_test/tester_dma.hh
M src/cpu/testers/gpu_ruby_test/tester_thread.cc
M src/cpu/testers/gpu_ruby_test/tester_thread.hh
M src/cpu/testers/memtest/MemTest.py
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/memtest/memtest.hh
M src/cpu/testers/rubytest/Check.cc
M src/cpu/testers/rubytest/Check.hh
M src/cpu/testers/rubytest/CheckTable.cc
M src/cpu/testers/rubytest/CheckTable.hh
M src/cpu/testers/rubytest/RubyTester.cc
M src/cpu/testers/rubytest/RubyTester.hh
M src/cpu/testers/rubytest/RubyTester.py
M src/cpu/testers/traffic_gen/BaseTrafficGen.py
M src/cpu/testers/traffic_gen/PyTrafficGen.py
M src/cpu/testers/traffic_gen/TrafficGen.py
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/testers/traffic_gen/base.hh
M src/cpu/testers/traffic_gen/base_gen.cc
M src/cpu/testers/traffic_gen/base_gen.hh
M src/cpu/testers/traffic_gen/dram_gen.cc
M src/cpu/testers/traffic_gen/dram_gen.hh
M src/cpu/testers/traffic_gen/dram_rot_gen.cc
M src/cpu/testers/traffic_gen/dram_rot_gen.hh
M src/cpu/testers/traffic_gen/exit_gen.cc
M src/cpu/testers/traffic_gen/exit_gen.hh
M src/cpu/testers/traffic_gen/hybrid_gen.cc
M src/cpu/testers/traffic_gen/hybrid_gen.hh
M src/cpu/testers/traffic_gen/idle_gen.cc
M src/cpu/testers/traffic_gen/idle_gen.hh
M src/cpu/testers/traffic_gen/linear_gen.cc
M src/cpu/testers/traffic_gen/linear_gen.hh
M src/cpu/testers/traffic_gen/nvm_gen.cc
M src/cpu/testers/traffic_gen/nvm_gen.hh
M src/cpu/testers/traffic_gen/pygen.cc
M src/cpu/testers/traffic_gen/pygen.hh
M src/cpu/testers/traffic_gen/random_gen.cc
M src/cpu/testers/traffic_gen/random_gen.hh
M src/cpu/testers/traffic_gen/stream_gen.cc
M src/cpu/testers/traffic_gen/stream_gen.hh
M src/cpu/testers/traffic_gen/strided_gen.cc
M src/cpu/testers/traffic_gen/strided_gen.hh
M src/cpu/testers/traffic_gen/trace_gen.cc
M src/cpu/testers/traffic_gen/trace_gen.hh
M src/cpu/testers/traffic_gen/traffic_gen.cc
M src/cpu/testers/traffic_gen/traffic_gen.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
M src/cpu/timebuf.hh
M src/cpu/timing_expr.cc
M src/cpu/timing_expr.hh
M src/cpu/trace/TraceCPU.py
M src/cpu/trace/trace_cpu.cc
M src/cpu/trace/trace_cpu.hh
M src/cpu/translation.hh
M src/cpu/utils.hh
M src/dev/BadDevice.py
M src/dev/Device.py
M src/dev/Platform.py
M src/dev/amdgpu/AMDGPU.py
M src/dev/amdgpu/amdgpu_device.cc
M src/dev/amdgpu/amdgpu_device.hh
M src/dev/arm/AbstractNVM.py
M src/dev/arm/Display.py
M src/dev/arm/Doorbell.py
M src/dev/arm/EnergyCtrl.py
M src/dev/arm/FlashDevice.py
M src/dev/arm/GenericTimer.py
M src/dev/arm/Gic.py
M src/dev/arm/NoMali.py
M src/dev/arm/RealView.py
M src/dev/arm/SMMUv3.py
M src/dev/arm/UFSHostDevice.py
M src/dev/arm/VirtIOMMIO.py
M src/dev/arm/a9scu.cc
M src/dev/arm/a9scu.hh
M src/dev/arm/abstract_nvm.hh
M src/dev/arm/amba.hh
M src/dev/arm/amba_device.cc
M src/dev/arm/amba_device.hh
M src/dev/arm/amba_fake.cc
M src/dev/arm/amba_fake.hh
M src/dev/arm/base_gic.cc
M src/dev/arm/base_gic.hh
M src/dev/arm/css/MHU.py
M src/dev/arm/css/Scmi.py
M src/dev/arm/css/Scp.py
M src/dev/arm/css/mhu.cc
M src/dev/arm/css/mhu.hh
M src/dev/arm/css/scmi_platform.cc
M src/dev/arm/css/scmi_platform.hh
M src/dev/arm/css/scmi_protocols.cc
M src/dev/arm/css/scmi_protocols.hh
M src/dev/arm/css/scp.hh
M src/dev/arm/display.cc
M src/dev/arm/display.hh
M src/dev/arm/doorbell.hh
M src/dev/arm/energy_ctrl.cc
M src/dev/arm/energy_ctrl.hh
M src/dev/arm/flash_device.cc
M src/dev/arm/flash_device.hh
M src/dev/arm/fvp_base_pwr_ctrl.cc
M src/dev/arm/fvp_base_pwr_ctrl.hh
M src/dev/arm/generic_timer.cc
M src/dev/arm/generic_timer.hh
M src/dev/arm/generic_timer_miscregs_types.hh
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v2.hh
M src/dev/arm/gic_v2m.cc
M src/dev/arm/gic_v2m.hh
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3.hh
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_cpu_interface.hh
M src/dev/arm/gic_v3_distributor.cc
M src/dev/arm/gic_v3_distributor.hh
M src/dev/arm/gic_v3_its.cc
M src/dev/arm/gic_v3_its.hh
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/gic_v3_redistributor.hh
M src/dev/arm/gpu_nomali.cc
M src/dev/arm/gpu_nomali.hh
M src/dev/arm/hdlcd.cc
M src/dev/arm/hdlcd.hh
M src/dev/arm/kmi.cc
M src/dev/arm/kmi.hh
M src/dev/arm/pci_host.cc
M src/dev/arm/pci_host.hh
M src/dev/arm/pl011.cc
M src/dev/arm/pl011.hh
M src/dev/arm/pl111.cc
M src/dev/arm/pl111.hh
M src/dev/arm/realview.cc
M src/dev/arm/realview.hh
M src/dev/arm/rtc_pl031.cc
M src/dev/arm/rtc_pl031.hh
M src/dev/arm/rv_ctrl.cc
M src/dev/arm/rv_ctrl.hh
M src/dev/arm/smmu_v3.cc
M src/dev/arm/smmu_v3.hh
M src/dev/arm/smmu_v3_caches.cc
M src/dev/arm/smmu_v3_caches.hh
M src/dev/arm/smmu_v3_cmdexec.cc
M src/dev/arm/smmu_v3_cmdexec.hh
M src/dev/arm/smmu_v3_defs.hh
M src/dev/arm/smmu_v3_deviceifc.cc
M src/dev/arm/smmu_v3_deviceifc.hh
M src/dev/arm/smmu_v3_events.cc
M src/dev/arm/smmu_v3_events.hh
M src/dev/arm/smmu_v3_ports.cc
M src/dev/arm/smmu_v3_ports.hh
M src/dev/arm/smmu_v3_proc.cc
M src/dev/arm/smmu_v3_proc.hh
M src/dev/arm/smmu_v3_ptops.cc
M src/dev/arm/smmu_v3_ptops.hh
M src/dev/arm/smmu_v3_transl.cc
M src/dev/arm/smmu_v3_transl.hh
M src/dev/arm/timer_cpulocal.cc
M src/dev/arm/timer_cpulocal.hh
M src/dev/arm/timer_sp804.cc
M src/dev/arm/timer_sp804.hh
M src/dev/arm/ufs_device.cc
M src/dev/arm/ufs_device.hh
M src/dev/arm/vgic.cc
M src/dev/arm/vgic.hh
M src/dev/arm/vio_mmio.cc
M src/dev/arm/vio_mmio.hh
M src/dev/arm/watchdog_generic.cc
M src/dev/arm/watchdog_generic.hh
M src/dev/arm/watchdog_sp805.cc
M src/dev/arm/watchdog_sp805.hh
M src/dev/baddev.cc
M src/dev/baddev.hh
M src/dev/dma_device.cc
M src/dev/dma_device.hh
M src/dev/hsa/HSADevice.py
M src/dev/hsa/HSADriver.py
M src/dev/hsa/hsa.h
M src/dev/hsa/hsa_packet.hh
M src/dev/hsa/hsa_packet_processor.cc
M src/dev/hsa/hsa_packet_processor.hh
M src/dev/hsa/hsa_queue.hh
M src/dev/hsa/hsa_signal.hh
M src/dev/hsa/hw_scheduler.cc
M src/dev/hsa/hw_scheduler.hh
M src/dev/hsa/kfd_event_defines.h
M src/dev/hsa/kfd_ioctl.h
M src/dev/i2c/I2C.py
M src/dev/i2c/bus.cc
M src/dev/i2c/bus.hh
M src/dev/i2c/device.hh
M src/dev/intel_8254_timer.cc
M src/dev/intel_8254_timer.hh
M src/dev/intpin.cc
M src/dev/intpin.hh
M src/dev/io_device.cc
M src/dev/io_device.hh
M src/dev/isa_fake.cc
M src/dev/isa_fake.hh
M src/dev/mc146818.cc
M src/dev/mc146818.hh
M src/dev/mips/Malta.py
M src/dev/mips/malta.cc
M src/dev/mips/malta.hh
M src/dev/mips/malta_cchip.cc
M src/dev/mips/malta_cchip.hh
M src/dev/mips/malta_io.cc
M src/dev/mips/malta_io.hh
M src/dev/net/Ethernet.py
M src/dev/net/dist_etherlink.cc
M src/dev/net/dist_etherlink.hh
M src/dev/net/dist_iface.cc
M src/dev/net/dist_iface.hh
M src/dev/net/dist_packet.hh
M src/dev/net/etherbus.cc
M src/dev/net/etherbus.hh
M src/dev/net/etherdevice.cc
M src/dev/net/etherdevice.hh
M src/dev/net/etherdump.cc
M src/dev/net/etherdump.hh
M src/dev/net/etherint.cc
M src/dev/net/etherint.hh
M src/dev/net/etherlink.cc
M src/dev/net/etherlink.hh
M src/dev/net/etherpkt.cc
M src/dev/net/etherpkt.hh
M src/dev/net/etherswitch.cc
M src/dev/net/etherswitch.hh
M src/dev/net/ethertap.cc
M src/dev/net/ethertap.hh
M src/dev/net/i8254xGBe.cc
M src/dev/net/i8254xGBe.hh
M src/dev/net/i8254xGBe_defs.hh
M src/dev/net/ns_gige.cc
M src/dev/net/ns_gige.hh
M src/dev/net/ns_gige_reg.h
M src/dev/net/pktfifo.cc
M src/dev/net/pktfifo.hh
M src/dev/net/sinic.cc
M src/dev/net/sinic.hh
M src/dev/net/sinicreg.hh
M src/dev/net/tcp_iface.cc
M src/dev/net/tcp_iface.hh
M src/dev/pci/CopyEngine.py
M src/dev/pci/PciDevice.py
M src/dev/pci/PciHost.py
M src/dev/pci/copy_engine.cc
M src/dev/pci/copy_engine.hh
M src/dev/pci/copy_engine_defs.hh
M src/dev/pci/device.cc
M src/dev/pci/device.hh
M src/dev/pci/host.cc
M src/dev/pci/host.hh
M src/dev/pci/types.hh
M src/dev/pixelpump.cc
M src/dev/pixelpump.hh
M src/dev/platform.cc
M src/dev/platform.hh
M src/dev/ps2/PS2.py
M src/dev/ps2/device.cc
M src/dev/ps2/device.hh
M src/dev/ps2/keyboard.cc
M src/dev/ps2/keyboard.hh
M src/dev/ps2/mouse.cc
M src/dev/ps2/mouse.hh
M src/dev/ps2/touchkit.cc
M src/dev/ps2/touchkit.hh
M src/dev/ps2/types.cc
M src/dev/ps2/types.hh
M src/dev/reg_bank.hh
M src/dev/reg_bank.test.cc
M src/dev/riscv/Clint.py
M src/dev/riscv/HiFive.py
M src/dev/riscv/Plic.py
M src/dev/riscv/PlicDevice.py
M src/dev/riscv/RTC.py
M src/dev/riscv/VirtIOMMIO.py
M src/dev/riscv/clint.cc
M src/dev/riscv/clint.hh
M src/dev/riscv/hifive.cc
M src/dev/riscv/hifive.hh
M src/dev/riscv/plic.cc
M src/dev/riscv/plic.hh
M src/dev/riscv/plic_device.cc
M src/dev/riscv/plic_device.hh
M src/dev/riscv/rtc.cc
M src/dev/riscv/rtc.hh
M src/dev/riscv/vio_mmio.cc
M src/dev/riscv/vio_mmio.hh
M src/dev/serial/Serial.py
M src/dev/serial/Terminal.py
M src/dev/serial/Uart.py
M src/dev/serial/serial.cc
M src/dev/serial/serial.hh
M src/dev/serial/simple.cc
M src/dev/serial/simple.hh
M src/dev/serial/terminal.cc
M src/dev/serial/terminal.hh
M src/dev/serial/uart.cc
M src/dev/serial/uart.hh
M src/dev/serial/uart8250.cc
M src/dev/serial/uart8250.hh
M src/dev/sparc/T1000.py
M src/dev/sparc/dtod.cc
M src/dev/sparc/dtod.hh
M src/dev/sparc/iob.cc
M src/dev/sparc/iob.hh
M src/dev/sparc/mm_disk.cc
M src/dev/sparc/mm_disk.hh
M src/dev/sparc/t1000.cc
M src/dev/sparc/t1000.hh
M src/dev/storage/DiskImage.py
M src/dev/storage/Ide.py
M src/dev/storage/SimpleDisk.py
M src/dev/storage/disk_image.cc
M src/dev/storage/disk_image.hh
M src/dev/storage/ide_ctrl.cc
M src/dev/storage/ide_ctrl.hh
M src/dev/storage/ide_disk.cc
M src/dev/storage/ide_disk.hh
M src/dev/storage/simple_disk.cc
M src/dev/storage/simple_disk.hh
M src/dev/virtio/VirtIO.py
M src/dev/virtio/VirtIO9P.py
M src/dev/virtio/VirtIOBlock.py
M src/dev/virtio/VirtIOConsole.py
M src/dev/virtio/base.cc
M src/dev/virtio/base.hh
M src/dev/virtio/block.cc
M src/dev/virtio/block.hh
M src/dev/virtio/console.cc
M src/dev/virtio/console.hh
M src/dev/virtio/fs9p.cc
M src/dev/virtio/fs9p.hh
M src/dev/virtio/pci.cc
M src/dev/virtio/pci.hh
M src/dev/x86/Cmos.py
M src/dev/x86/I8042.py
M src/dev/x86/I82094AA.py
M src/dev/x86/I8237.py
M src/dev/x86/I8254.py
M src/dev/x86/I8259.py
M src/dev/x86/Pc.py
M src/dev/x86/PcSpeaker.py
M src/dev/x86/SouthBridge.py
M src/dev/x86/cmos.cc
M src/dev/x86/cmos.hh
M src/dev/x86/i8042.cc
M src/dev/x86/i8042.hh
M src/dev/x86/i82094aa.cc
M src/dev/x86/i82094aa.hh
M src/dev/x86/i8237.cc
M src/dev/x86/i8237.hh
M src/dev/x86/i8254.cc
M src/dev/x86/i8254.hh
M src/dev/x86/i8259.cc
M src/dev/x86/i8259.hh
M src/dev/x86/intdev.hh
M src/dev/x86/pc.cc
M src/dev/x86/pc.hh
M src/dev/x86/south_bridge.cc
M src/dev/x86/south_bridge.hh
M src/dev/x86/speaker.cc
M src/dev/x86/speaker.hh
M src/gpu-compute/GPU.py
M src/gpu-compute/LdsState.py
M src/gpu-compute/X86GPUTLB.py
M src/gpu-compute/comm.cc
M src/gpu-compute/comm.hh
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/dispatcher.cc
M src/gpu-compute/dispatcher.hh
M src/gpu-compute/dyn_pool_manager.cc
M src/gpu-compute/dyn_pool_manager.hh
M src/gpu-compute/exec_stage.cc
M src/gpu-compute/exec_stage.hh
M src/gpu-compute/fetch_stage.cc
M src/gpu-compute/fetch_stage.hh
M src/gpu-compute/fetch_unit.cc
M src/gpu-compute/fetch_unit.hh
M src/gpu-compute/global_memory_pipeline.cc
M src/gpu-compute/global_memory_pipeline.hh
M src/gpu-compute/gpu_command_processor.cc
M src/gpu-compute/gpu_command_processor.hh
M src/gpu-compute/gpu_compute_driver.cc
M src/gpu-compute/gpu_compute_driver.hh
M src/gpu-compute/gpu_dyn_inst.cc
M src/gpu-compute/gpu_dyn_inst.hh
M src/gpu-compute/gpu_exec_context.cc
M src/gpu-compute/gpu_exec_context.hh
M src/gpu-compute/gpu_static_inst.cc
M src/gpu-compute/gpu_static_inst.hh
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/hsa_queue_entry.hh
M src/gpu-compute/kernel_code.hh
M src/gpu-compute/lds_state.cc
M src/gpu-compute/lds_state.hh
M src/gpu-compute/local_memory_pipeline.cc
M src/gpu-compute/local_memory_pipeline.hh
M src/gpu-compute/misc.hh
M src/gpu-compute/of_scheduling_policy.hh
M src/gpu-compute/operand_info.hh
M src/gpu-compute/pool_manager.cc
M src/gpu-compute/pool_manager.hh
M src/gpu-compute/register_file.cc
M src/gpu-compute/register_file.hh
M src/gpu-compute/register_manager.cc
M src/gpu-compute/register_manager.hh
M src/gpu-compute/register_manager_policy.hh
M src/gpu-compute/rr_scheduling_policy.hh
M src/gpu-compute/scalar_memory_pipeline.cc
M src/gpu-compute/scalar_memory_pipeline.hh
M src/gpu-compute/scalar_register_file.cc
M src/gpu-compute/scalar_register_file.hh
M src/gpu-compute/schedule_stage.cc
M src/gpu-compute/schedule_stage.hh
M src/gpu-compute/scheduler.cc
M src/gpu-compute/scheduler.hh
M src/gpu-compute/scheduling_policy.hh
M src/gpu-compute/scoreboard_check_stage.cc
M src/gpu-compute/scoreboard_check_stage.hh
M src/gpu-compute/shader.cc
M src/gpu-compute/shader.hh
M src/gpu-compute/simple_pool_manager.cc
M src/gpu-compute/simple_pool_manager.hh
M src/gpu-compute/static_register_manager_policy.cc
M src/gpu-compute/static_register_manager_policy.hh
M src/gpu-compute/tlb_coalescer.cc
M src/gpu-compute/tlb_coalescer.hh
M src/gpu-compute/vector_register_file.cc
M src/gpu-compute/vector_register_file.hh
M src/gpu-compute/wavefront.cc
M src/gpu-compute/wavefront.hh
M src/kern/freebsd/events.cc
M src/kern/freebsd/events.hh
M src/kern/freebsd/freebsd.hh
M src/kern/linux/events.cc
M src/kern/linux/events.hh
M src/kern/linux/flag_tables.hh
M src/kern/linux/helpers.cc
M src/kern/linux/helpers.hh
M src/kern/linux/linux.cc
M src/kern/linux/linux.hh
M src/kern/linux/printk.cc
M src/kern/linux/printk.hh
M src/kern/operatingsystem.cc
M src/kern/operatingsystem.hh
M src/kern/solaris/solaris.hh
M src/kern/system_events.cc
M src/kern/system_events.hh
M src/learning_gem5/part2/HelloObject.py
M src/learning_gem5/part2/SimpleCache.py
M src/learning_gem5/part2/SimpleMemobj.py
M src/learning_gem5/part2/SimpleObject.py
M src/learning_gem5/part2/goodbye_object.cc
M src/learning_gem5/part2/goodbye_object.hh
M src/learning_gem5/part2/hello_object.cc
M src/learning_gem5/part2/hello_object.hh
M src/learning_gem5/part2/simple_cache.cc
M src/learning_gem5/part2/simple_cache.hh
M src/learning_gem5/part2/simple_memobj.cc
M src/learning_gem5/part2/simple_memobj.hh
M src/learning_gem5/part2/simple_object.cc
M src/learning_gem5/part2/simple_object.hh
M src/mem/AbstractMemory.py
M src/mem/AddrMapper.py
M src/mem/Bridge.py
M src/mem/CfiMemory.py
M src/mem/CommMonitor.py
M src/mem/DRAMInterface.py
M src/mem/DRAMSim2.py
M src/mem/DRAMsim3.py
M src/mem/ExternalMaster.py
M src/mem/ExternalSlave.py
M src/mem/HMCController.py
M src/mem/MemChecker.py
M src/mem/MemCtrl.py
M src/mem/MemDelay.py
M src/mem/MemInterface.py
M src/mem/MemObject.py
M src/mem/NVMInterface.py
M src/mem/SerialLink.py
M src/mem/SimpleMemory.py
M src/mem/XBar.py
M src/mem/abstract_mem.cc
M src/mem/abstract_mem.hh
M src/mem/addr_mapper.cc
M src/mem/addr_mapper.hh
M src/mem/backdoor.hh
M src/mem/bridge.cc
M src/mem/bridge.hh
M src/mem/cache/Cache.py
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
M src/mem/cache/cache_blk.cc
M src/mem/cache/cache_blk.hh
M src/mem/cache/compressors/Compressors.py
M src/mem/cache/compressors/base.cc
M src/mem/cache/compressors/base.hh
M src/mem/cache/compressors/base_delta.cc
M src/mem/cache/compressors/base_delta.hh
M src/mem/cache/compressors/base_delta_impl.hh
M src/mem/cache/compressors/base_dictionary_compressor.cc
M src/mem/cache/compressors/cpack.cc
M src/mem/cache/compressors/cpack.hh
M src/mem/cache/compressors/dictionary_compressor.hh
M src/mem/cache/compressors/dictionary_compressor_impl.hh
M src/mem/cache/compressors/encoders/base.hh
M src/mem/cache/compressors/encoders/huffman.cc
M src/mem/cache/compressors/encoders/huffman.hh
M src/mem/cache/compressors/fpc.cc
M src/mem/cache/compressors/fpc.hh
M src/mem/cache/compressors/fpcd.cc
M src/mem/cache/compressors/fpcd.hh
M src/mem/cache/compressors/frequent_values.cc
M src/mem/cache/compressors/frequent_values.hh
M src/mem/cache/compressors/multi.cc
M src/mem/cache/compressors/multi.hh
M src/mem/cache/compressors/perfect.cc
M src/mem/cache/compressors/perfect.hh
M src/mem/cache/compressors/repeated_qwords.cc
M src/mem/cache/compressors/repeated_qwords.hh
M src/mem/cache/compressors/zero.cc
M src/mem/cache/compressors/zero.hh
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/mshr_queue.cc
M src/mem/cache/mshr_queue.hh
M src/mem/cache/noncoherent_cache.cc
M src/mem/cache/noncoherent_cache.hh
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/access_map_pattern_matching.cc
M src/mem/cache/prefetch/access_map_pattern_matching.hh
M src/mem/cache/prefetch/associative_set.hh
M src/mem/cache/prefetch/associative_set_impl.hh
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/bop.cc
M src/mem/cache/prefetch/bop.hh
M src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
M src/mem/cache/prefetch/delta_correlating_prediction_tables.hh
M src/mem/cache/prefetch/indirect_memory.cc
M src/mem/cache/prefetch/indirect_memory.hh
M src/mem/cache/prefetch/irregular_stream_buffer.cc
M src/mem/cache/prefetch/irregular_stream_buffer.hh
M src/mem/cache/prefetch/multi.cc
M src/mem/cache/prefetch/multi.hh
M src/mem/cache/prefetch/pif.cc
M src/mem/cache/prefetch/pif.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
M src/mem/cache/prefetch/sbooe.cc
M src/mem/cache/prefetch/sbooe.hh
M src/mem/cache/prefetch/signature_path.cc
M src/mem/cache/prefetch/signature_path.hh
M src/mem/cache/prefetch/signature_path_v2.cc
M src/mem/cache/prefetch/signature_path_v2.hh
M src/mem/cache/prefetch/slim_ampm.cc
M src/mem/cache/prefetch/slim_ampm.hh
M src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc
M src/mem/cache/prefetch/spatio_temporal_memory_streaming.hh
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/prefetch/tagged.cc
M src/mem/cache/prefetch/tagged.hh
M src/mem/cache/queue.hh
M src/mem/cache/queue_entry.hh
M src/mem/cache/replacement_policies/ReplacementPolicies.py
M src/mem/cache/replacement_policies/base.hh
M src/mem/cache/replacement_policies/bip_rp.cc
M src/mem/cache/replacement_policies/bip_rp.hh
M src/mem/cache/replacement_policies/brrip_rp.cc
M src/mem/cache/replacement_policies/brrip_rp.hh
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.hh
M src/mem/cache/replacement_policies/lfu_rp.cc
M src/mem/cache/replacement_policies/lfu_rp.hh
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/lru_rp.hh
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.hh
M src/mem/cache/replacement_policies/random_rp.cc
M src/mem/cache/replacement_policies/random_rp.hh
M src/mem/cache/replacement_policies/replaceable_entry.hh
M src/mem/cache/replacement_policies/second_chance_rp.cc
M src/mem/cache/replacement_policies/second_chance_rp.hh
M src/mem/cache/replacement_policies/tree_plru_rp.cc
M src/mem/cache/replacement_policies/tree_plru_rp.hh
M src/mem/cache/replacement_policies/weighted_lru_rp.cc
M src/mem/cache/replacement_policies/weighted_lru_rp.hh
M src/mem/cache/tags/Tags.py
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/compressed_tags.cc
M src/mem/cache/tags/compressed_tags.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
M src/mem/cache/tags/indexing_policies/IndexingPolicies.py
M src/mem/cache/tags/indexing_policies/base.cc
M src/mem/cache/tags/indexing_policies/base.hh
M src/mem/cache/tags/indexing_policies/set_associative.cc
M src/mem/cache/tags/indexing_policies/set_associative.hh
M src/mem/cache/tags/indexing_policies/skewed_associative.cc
M src/mem/cache/tags/indexing_policies/skewed_associative.hh
M src/mem/cache/tags/sector_blk.cc
M src/mem/cache/tags/sector_blk.hh
M src/mem/cache/tags/sector_tags.cc
M src/mem/cache/tags/sector_tags.hh
M src/mem/cache/tags/super_blk.cc
M src/mem/cache/tags/super_blk.hh
M src/mem/cache/tags/tagged_entry.hh
M src/mem/cache/write_queue.cc
M src/mem/cache/write_queue.hh
M src/mem/cache/write_queue_entry.cc
M src/mem/cache/write_queue_entry.hh
M src/mem/cfi_mem.cc
M src/mem/cfi_mem.hh
M src/mem/coherent_xbar.cc
M src/mem/coherent_xbar.hh
M src/mem/comm_monitor.cc
M src/mem/comm_monitor.hh
M src/mem/drampower.cc
M src/mem/drampower.hh
M src/mem/dramsim2.cc
M src/mem/dramsim2.hh
M src/mem/dramsim2_wrapper.cc
M src/mem/dramsim2_wrapper.hh
M src/mem/dramsim3.cc
M src/mem/dramsim3.hh
M src/mem/dramsim3_wrapper.cc
M src/mem/dramsim3_wrapper.hh
M src/mem/external_master.cc
M src/mem/external_master.hh
M src/mem/external_slave.cc
M src/mem/external_slave.hh
M src/mem/hmc_controller.cc
M src/mem/hmc_controller.hh
M src/mem/htm.cc
M src/mem/htm.hh
M src/mem/mem_checker.cc
M src/mem/mem_checker.hh
M src/mem/mem_checker_monitor.cc
M src/mem/mem_checker_monitor.hh
M src/mem/mem_ctrl.cc
M src/mem/mem_ctrl.hh
M src/mem/mem_delay.cc
M src/mem/mem_delay.hh
M src/mem/mem_interface.cc
M src/mem/mem_interface.hh
M src/mem/mem_object.hh
M src/mem/mem_requestor.hh
M src/mem/multi_level_page_table.hh
M src/mem/noncoherent_xbar.cc
M src/mem/noncoherent_xbar.hh
M src/mem/packet.cc
M src/mem/packet.hh
M src/mem/packet_access.hh
M src/mem/packet_queue.cc
M src/mem/packet_queue.hh
M src/mem/page_table.cc
M src/mem/page_table.hh
M src/mem/physical.cc
M src/mem/physical.hh
M src/mem/port.cc
M src/mem/port.hh
M src/mem/port_proxy.cc
M src/mem/port_proxy.hh
M src/mem/probes/BaseMemProbe.py
M src/mem/probes/MemFootprintProbe.py
M src/mem/probes/MemTraceProbe.py
M src/mem/probes/StackDistProbe.py
M src/mem/probes/base.cc
M src/mem/probes/base.hh
M src/mem/probes/mem_footprint.cc
M src/mem/probes/mem_footprint.hh
M src/mem/probes/mem_trace.cc
M src/mem/probes/mem_trace.hh
M src/mem/probes/stack_dist.cc
M src/mem/probes/stack_dist.hh
M src/mem/protocol/atomic.cc
M src/mem/protocol/atomic.hh
M src/mem/protocol/functional.cc
M src/mem/protocol/functional.hh
M src/mem/protocol/timing.cc
M src/mem/protocol/timing.hh
M src/mem/qos/QoSMemCtrl.py
M src/mem/qos/QoSMemSinkCtrl.py
M src/mem/qos/QoSMemSinkInterface.py
M src/mem/qos/QoSPolicy.py
M src/mem/qos/QoSTurnaround.py
M src/mem/qos/mem_ctrl.cc
M src/mem/qos/mem_ctrl.hh
M src/mem/qos/mem_sink.cc
M src/mem/qos/mem_sink.hh
M src/mem/qos/policy.cc
M src/mem/qos/policy.hh
M src/mem/qos/policy_fixed_prio.cc
M src/mem/qos/policy_fixed_prio.hh
M src/mem/qos/policy_pf.cc
M src/mem/qos/policy_pf.hh
M src/mem/qos/q_policy.cc
M src/mem/qos/q_policy.hh
M src/mem/qos/turnaround_policy.hh
M src/mem/qos/turnaround_policy_ideal.cc
M src/mem/qos/turnaround_policy_ideal.hh
M src/mem/qport.hh
M src/mem/request.hh
M src/mem/ruby/common/Address.cc
M src/mem/ruby/common/Address.hh
M src/mem/ruby/common/BoolVec.cc
M src/mem/ruby/common/BoolVec.hh
M src/mem/ruby/common/Consumer.cc
M src/mem/ruby/common/Consumer.hh
M src/mem/ruby/common/DataBlock.cc
M src/mem/ruby/common/DataBlock.hh
M src/mem/ruby/common/ExpectedMap.hh
M src/mem/ruby/common/Histogram.cc
M src/mem/ruby/common/Histogram.hh
M src/mem/ruby/common/IntVec.cc
M src/mem/ruby/common/IntVec.hh
M src/mem/ruby/common/MachineID.hh
M src/mem/ruby/common/NetDest.cc
M src/mem/ruby/common/NetDest.hh
M src/mem/ruby/common/Set.hh
M src/mem/ruby/common/SubBlock.cc
M src/mem/ruby/common/SubBlock.hh
M src/mem/ruby/common/TriggerQueue.hh
M src/mem/ruby/common/TypeDefines.hh
M src/mem/ruby/common/WriteMask.cc
M src/mem/ruby/common/WriteMask.hh
M src/mem/ruby/network/BasicLink.cc
M src/mem/ruby/network/BasicLink.hh
M src/mem/ruby/network/BasicLink.py
M src/mem/ruby/network/BasicRouter.cc
M src/mem/ruby/network/BasicRouter.hh
M src/mem/ruby/network/BasicRouter.py
M src/mem/ruby/network/MessageBuffer.cc
M src/mem/ruby/network/MessageBuffer.hh
M src/mem/ruby/network/MessageBuffer.py
M src/mem/ruby/network/Network.cc
M src/mem/ruby/network/Network.hh
M src/mem/ruby/network/Network.py
M src/mem/ruby/network/Topology.cc
M src/mem/ruby/network/Topology.hh
M src/mem/ruby/network/dummy_port.hh
M src/mem/ruby/network/fault_model/FaultModel.cc
M src/mem/ruby/network/fault_model/FaultModel.hh
M src/mem/ruby/network/fault_model/FaultModel.py
M src/mem/ruby/network/garnet/CommonTypes.hh
M src/mem/ruby/network/garnet/Credit.cc
M src/mem/ruby/network/garnet/Credit.hh
M src/mem/ruby/network/garnet/CreditLink.hh
M src/mem/ruby/network/garnet/CrossbarSwitch.cc
M src/mem/ruby/network/garnet/CrossbarSwitch.hh
M src/mem/ruby/network/garnet/GarnetLink.cc
M src/mem/ruby/network/garnet/GarnetLink.hh
M src/mem/ruby/network/garnet/GarnetLink.py
M src/mem/ruby/network/garnet/GarnetNetwork.cc
M src/mem/ruby/network/garnet/GarnetNetwork.hh
M src/mem/ruby/network/garnet/GarnetNetwork.py
M src/mem/ruby/network/garnet/InputUnit.cc
M src/mem/ruby/network/garnet/InputUnit.hh
M src/mem/ruby/network/garnet/NetworkBridge.cc
M src/mem/ruby/network/garnet/NetworkBridge.hh
M src/mem/ruby/network/garnet/NetworkInterface.cc
M src/mem/ruby/network/garnet/NetworkInterface.hh
M src/mem/ruby/network/garnet/NetworkLink.cc
M src/mem/ruby/network/garnet/NetworkLink.hh
M src/mem/ruby/network/garnet/OutVcState.cc
M src/mem/ruby/network/garnet/OutVcState.hh
M src/mem/ruby/network/garnet/OutputUnit.cc
M src/mem/ruby/network/garnet/OutputUnit.hh
M src/mem/ruby/network/garnet/Router.cc
M src/mem/ruby/network/garnet/Router.hh
M src/mem/ruby/network/garnet/RoutingUnit.cc
M src/mem/ruby/network/garnet/RoutingUnit.hh
M src/mem/ruby/network/garnet/SwitchAllocator.cc
M src/mem/ruby/network/garnet/SwitchAllocator.hh
M src/mem/ruby/network/garnet/VirtualChannel.cc
M src/mem/ruby/network/garnet/VirtualChannel.hh
M src/mem/ruby/network/garnet/flit.cc
M src/mem/ruby/network/garnet/flit.hh
M src/mem/ruby/network/garnet/flitBuffer.cc
M src/mem/ruby/network/garnet/flitBuffer.hh
M src/mem/ruby/network/simple/PerfectSwitch.cc
M src/mem/ruby/network/simple/PerfectSwitch.hh
M src/mem/ruby/network/simple/SimpleLink.cc
M src/mem/ruby/network/simple/SimpleLink.hh
M src/mem/ruby/network/simple/SimpleLink.py
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/SimpleNetwork.hh
M src/mem/ruby/network/simple/SimpleNetwork.py
M src/mem/ruby/network/simple/Switch.cc
M src/mem/ruby/network/simple/Switch.hh
M src/mem/ruby/network/simple/Throttle.cc
M src/mem/ruby/network/simple/Throttle.hh
M src/mem/ruby/profiler/AccessTraceForAddress.cc
M src/mem/ruby/profiler/AccessTraceForAddress.hh
M src/mem/ruby/profiler/AddressProfiler.cc
M src/mem/ruby/profiler/AddressProfiler.hh
M src/mem/ruby/profiler/Profiler.cc
M src/mem/ruby/profiler/Profiler.hh
M src/mem/ruby/profiler/StoreTrace.cc
M src/mem/ruby/profiler/StoreTrace.hh
M src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
M src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/slicc_interface/Controller.py
M src/mem/ruby/slicc_interface/Message.hh
M src/mem/ruby/slicc_interface/RubyRequest.cc
M src/mem/ruby/slicc_interface/RubyRequest.hh
M src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
M src/mem/ruby/structures/BankedArray.cc
M src/mem/ruby/structures/BankedArray.hh
M src/mem/ruby/structures/CacheMemory.cc
M src/mem/ruby/structures/CacheMemory.hh
M src/mem/ruby/structures/DirectoryMemory.cc
M src/mem/ruby/structures/DirectoryMemory.hh
M src/mem/ruby/structures/DirectoryMemory.py
M src/mem/ruby/structures/PerfectCacheMemory.hh
M src/mem/ruby/structures/PersistentTable.cc
M src/mem/ruby/structures/PersistentTable.hh
M src/mem/ruby/structures/RubyCache.py
M src/mem/ruby/structures/RubyPrefetcher.cc
M src/mem/ruby/structures/RubyPrefetcher.hh
M src/mem/ruby/structures/RubyPrefetcher.py
M src/mem/ruby/structures/TBEStorage.cc
M src/mem/ruby/structures/TBEStorage.hh
M src/mem/ruby/structures/TBETable.hh
M src/mem/ruby/structures/TimerTable.cc
M src/mem/ruby/structures/TimerTable.hh
M src/mem/ruby/structures/WireBuffer.cc
M src/mem/ruby/structures/WireBuffer.hh
M src/mem/ruby/structures/WireBuffer.py
M src/mem/ruby/system/CacheRecorder.cc
M src/mem/ruby/system/CacheRecorder.hh
M src/mem/ruby/system/DMASequencer.cc
M src/mem/ruby/system/DMASequencer.hh
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/GPUCoalescer.py
M src/mem/ruby/system/HTMSequencer.cc
M src/mem/ruby/system/HTMSequencer.hh
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/mem/ruby/system/RubyPortProxy.cc
M src/mem/ruby/system/RubyPortProxy.hh
M src/mem/ruby/system/RubySystem.cc
M src/mem/ruby/system/RubySystem.hh
M src/mem/ruby/system/RubySystem.py
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
M src/mem/ruby/system/Sequencer.py
M src/mem/ruby/system/VIPERCoalescer.cc
M src/mem/ruby/system/VIPERCoalescer.hh
M src/mem/ruby/system/VIPERCoalescer.py
M src/mem/se_translating_port_proxy.cc
M src/mem/se_translating_port_proxy.hh
M src/mem/serial_link.cc
M src/mem/serial_link.hh
M src/mem/simple_mem.cc
M src/mem/simple_mem.hh
M src/mem/snoop_filter.cc
M src/mem/snoop_filter.hh
M src/mem/stack_dist_calc.cc
M src/mem/stack_dist_calc.hh
M src/mem/token_port.cc
M src/mem/token_port.hh
M src/mem/tport.cc
M src/mem/tport.hh
M src/mem/translating_port_proxy.cc
M src/mem/translating_port_proxy.hh
M src/mem/xbar.cc
M src/mem/xbar.hh
M src/python/m5/SimObject.py
M src/python/pybind11/core.cc
M src/python/pybind11/core.hh
M src/python/pybind11/debug.cc
M src/python/pybind11/event.cc
M src/python/pybind11/object_file.cc
M src/python/pybind11/pybind.hh
M src/python/pybind11/stats.cc
M src/sim/ClockDomain.py
M src/sim/ClockedObject.py
M src/sim/DVFSHandler.py
M src/sim/InstTracer.py
M src/sim/PowerDomain.py
M src/sim/PowerState.py
M src/sim/Process.py
M src/sim/RedirectPath.py
M src/sim/Root.py
M src/sim/SubSystem.py
M src/sim/System.py
M src/sim/TickedObject.py
M src/sim/VoltageDomain.py
M src/sim/Workload.py
M src/sim/async.cc
M src/sim/async.hh
M src/sim/aux_vector.hh
M src/sim/backtrace.hh
M src/sim/backtrace_glibc.cc
M src/sim/backtrace_none.cc
M src/sim/byteswap.hh
M src/sim/byteswap.test.cc
M src/sim/clock_domain.cc
M src/sim/clock_domain.hh
M src/sim/clocked_object.cc
M src/sim/clocked_object.hh
M src/sim/core.cc
M src/sim/core.hh
M src/sim/cur_tick.cc
M src/sim/cur_tick.hh
M src/sim/cxx_config.cc
M src/sim/cxx_config.hh
M src/sim/cxx_config_ini.cc
M src/sim/cxx_config_ini.hh
M src/sim/cxx_manager.cc
M src/sim/cxx_manager.hh
M src/sim/debug.cc
M src/sim/debug.hh
M src/sim/drain.cc
M src/sim/drain.hh
M src/sim/dvfs_handler.cc
M src/sim/dvfs_handler.hh
M src/sim/emul_driver.hh
M src/sim/eventq.cc
M src/sim/eventq.hh
M src/sim/faults.cc
M src/sim/faults.hh
M src/sim/fd_array.cc
M src/sim/fd_array.hh
M src/sim/fd_entry.cc
M src/sim/fd_entry.hh
M src/sim/full_system.hh
M src/sim/futex_map.cc
M src/sim/futex_map.hh
M src/sim/global_event.cc
M src/sim/global_event.hh
M src/sim/guest_abi.hh
M src/sim/guest_abi.test.cc
M src/sim/guest_abi/definition.hh
M src/sim/guest_abi/dispatch.hh
M src/sim/guest_abi/layout.hh
M src/sim/guest_abi/varargs.hh
M src/sim/init.cc
M src/sim/init.hh
M src/sim/init_signals.cc
M src/sim/init_signals.hh
M src/sim/insttracer.hh
M src/sim/kernel_workload.cc
M src/sim/kernel_workload.hh
M src/sim/linear_solver.cc
M src/sim/linear_solver.hh
M src/sim/main.cc
M src/sim/mathexpr.cc
M src/sim/mathexpr.hh
M src/sim/mem_pool.cc
M src/sim/mem_pool.hh
M src/sim/mem_state.cc
M src/sim/mem_state.hh
M src/sim/port.cc
M src/sim/port.hh
M src/sim/power/MathExprPowerModel.py
M src/sim/power/PowerModel.py
M src/sim/power/PowerModelState.py
M src/sim/power/ThermalDomain.py
M src/sim/power/ThermalModel.py
M src/sim/power/mathexpr_powermodel.cc
M src/sim/power/mathexpr_powermodel.hh
M src/sim/power/power_model.cc
M src/sim/power/power_model.hh
M src/sim/power/thermal_domain.cc
M src/sim/power/thermal_domain.hh
M src/sim/power/thermal_entity.hh
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
M src/sim/power/thermal_node.cc
M src/sim/power/thermal_node.hh
M src/sim/power_domain.cc
M src/sim/power_domain.hh
M src/sim/power_state.cc
M src/sim/power_state.hh
M src/sim/probe/Probe.py
M src/sim/probe/mem.hh
M src/sim/probe/pmu.hh
M src/sim/probe/probe.cc
M src/sim/probe/probe.hh
M src/sim/process.cc
M src/sim/process.hh
M src/sim/process_impl.hh
M src/sim/proxy_ptr.hh
M src/sim/proxy_ptr.test.cc
M src/sim/pseudo_inst.cc
M src/sim/pseudo_inst.hh
M src/sim/py_interact.cc
M src/sim/py_interact.hh
M src/sim/python.cc
M src/sim/redirect_path.cc
M src/sim/redirect_path.hh
M src/sim/root.cc
M src/sim/root.hh
M src/sim/se_signal.cc
M src/sim/se_signal.hh
M src/sim/se_workload.cc
M src/sim/se_workload.hh
M src/sim/serialize.cc
M src/sim/serialize.hh
M src/sim/serialize_handlers.hh
M src/sim/sim_events.cc
M src/sim/sim_events.hh
M src/sim/sim_exit.hh
M src/sim/sim_object.cc
M src/sim/sim_object.hh
M src/sim/simulate.cc
M src/sim/simulate.hh
M src/sim/stat_control.cc
M src/sim/stat_control.hh
M src/sim/stat_register.cc
M src/sim/stat_register.hh
M src/sim/stats.cc
M src/sim/stats.hh
M src/sim/sub_system.cc
M src/sim/sub_system.hh
M src/sim/syscall_abi.hh
M src/sim/syscall_desc.cc
M src/sim/syscall_desc.hh
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
M src/sim/syscall_emul_buf.hh
M src/sim/syscall_return.hh
M src/sim/system.cc
M src/sim/system.hh
M src/sim/ticked_object.cc
M src/sim/ticked_object.hh
M src/sim/vma.cc
M src/sim/vma.hh
M src/sim/voltage_domain.cc
M src/sim/voltage_domain.hh
M src/sim/workload.cc
M src/sim/workload.hh
2,028 files changed, 9,001 insertions(+), 543 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/46323
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia53d404ec79c46edaa98f654e23bc3b0e179fe2d
Gerrit-Change-Number: 46323
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
