Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47100 )
Change subject: arch-vega: Simplify VecRegContainer in Vega
......................................................................
arch-vega: Simplify VecRegContainer in Vega
VecRegContainer was simplified while this patch was still in review and
these files were not changed.
Change-Id: I350ac94dc14e3ba0fb9619fa084e80cc8cbd7660
---
M src/arch/amdgpu/vega/gpu_registers.hh
M src/arch/amdgpu/vega/operand.hh
2 files changed, 6 insertions(+), 33 deletions(-)
diff --git a/src/arch/amdgpu/vega/gpu_registers.hh
b/src/arch/amdgpu/vega/gpu_registers.hh
index 0d2f948..6118fb2 100644
--- a/src/arch/amdgpu/vega/gpu_registers.hh
+++ b/src/arch/amdgpu/vega/gpu_registers.hh
@@ -174,33 +174,10 @@
*/
const int RegSizeDWords = sizeof(VecElemU32) / DWordSize;
- // typedefs for the various sizes/types of vector regs
- using VecRegU8 = ::VecRegT<VecElemU8, NumVecElemPerVecReg, false>;
- using VecRegI8 = ::VecRegT<VecElemI8, NumVecElemPerVecReg, false>;
- using VecRegU16 = ::VecRegT<VecElemU16, NumVecElemPerVecReg, false>;
- using VecRegI16 = ::VecRegT<VecElemI16, NumVecElemPerVecReg, false>;
- using VecRegU32 = ::VecRegT<VecElemU32, NumVecElemPerVecReg, false>;
- using VecRegI32 = ::VecRegT<VecElemI32, NumVecElemPerVecReg, false>;
- using VecRegF32 = ::VecRegT<VecElemF32, NumVecElemPerVecReg, false>;
- using VecRegU64 = ::VecRegT<VecElemU64, NumVecElemPerVecReg, false>;
- using VecRegI64 = ::VecRegT<VecElemI64, NumVecElemPerVecReg, false>;
- using VecRegF64 = ::VecRegT<VecElemF64, NumVecElemPerVecReg, false>;
- // non-writeable versions of vector regs
- using ConstVecRegU8 = ::VecRegT<VecElemU8, NumVecElemPerVecReg, true>;
- using ConstVecRegI8 = ::VecRegT<VecElemI8, NumVecElemPerVecReg, true>;
- using ConstVecRegU16 = ::VecRegT<VecElemU16, NumVecElemPerVecReg,
true>;
- using ConstVecRegI16 = ::VecRegT<VecElemI16, NumVecElemPerVecReg,
true>;
- using ConstVecRegU32 = ::VecRegT<VecElemU32, NumVecElemPerVecReg,
true>;
- using ConstVecRegI32 = ::VecRegT<VecElemI32, NumVecElemPerVecReg,
true>;
- using ConstVecRegF32 = ::VecRegT<VecElemF32, NumVecElemPerVecReg,
true>;
- using ConstVecRegU64 = ::VecRegT<VecElemU64, NumVecElemPerVecReg,
true>;
- using ConstVecRegI64 = ::VecRegT<VecElemI64, NumVecElemPerVecReg,
true>;
- using ConstVecRegF64 = ::VecRegT<VecElemF64, NumVecElemPerVecReg,
true>;
-
- using VecRegContainerU8 = VecRegU8::Container;
- using VecRegContainerU16 = VecRegU16::Container;
- using VecRegContainerU32 = VecRegU32::Container;
- using VecRegContainerU64 = VecRegU64::Container;
+ using VecRegContainerU32 =
+ VecRegContainer<sizeof(VecElemU32) * NumVecElemPerVecReg>;
+ using VecRegContainerU64 =
+ VecRegContainer<sizeof(VecElemU64) * NumVecElemPerVecReg>;
struct StatusReg
{
diff --git a/src/arch/amdgpu/vega/operand.hh
b/src/arch/amdgpu/vega/operand.hh
index a4517ea..bb89fb3 100644
--- a/src/arch/amdgpu/vega/operand.hh
+++ b/src/arch/amdgpu/vega/operand.hh
@@ -326,12 +326,8 @@
scRegData.read();
}
- using VecRegCont = typename std::conditional_t<NumDwords == 2,
- VecRegContainerU64, typename
std::conditional_t<sizeof(DataType)
- == sizeof(VecElemU16), VecRegContainerU16,
- typename std::conditional_t<sizeof(DataType)
- == sizeof(VecElemU8), VecRegContainerU8,
- VecRegContainerU32>>>;
+ using VecRegCont =
+ VecRegContainer<sizeof(DataType) * NumVecElemPerVecReg>;
/**
* whether this operand a scalar or not.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I350ac94dc14e3ba0fb9619fa084e80cc8cbd7660
Gerrit-Change-Number: 47100
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-MessageType: newchange
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