Guokai Chen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47119 )
Change subject: arch-riscv: Fix unusable RAS on RISC-V
......................................................................
arch-riscv: Fix unusable RAS on RISC-V
This change adds IsReturn flag for RISC-V ret instructions in decoder
and fixes target overwriting in buildRetPC.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1012
Change-Id: I30f4b56fdca760986b503ce9f40d57d703a050a7
---
M src/arch/riscv/insts/static_inst.hh
M src/arch/riscv/isa/decoder.isa
2 files changed, 50 insertions(+), 20 deletions(-)
diff --git a/src/arch/riscv/insts/static_inst.hh
b/src/arch/riscv/insts/static_inst.hh
index 1c9c616..455037c 100644
--- a/src/arch/riscv/insts/static_inst.hh
+++ b/src/arch/riscv/insts/static_inst.hh
@@ -61,7 +61,6 @@
{
PCState retPC = callPC;
retPC.advance();
- retPC.pc(curPC.npc());
return retPC;
}
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 823698c..c55bba9 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -306,13 +306,22 @@
}
0x4: decode CFUNCT1 {
0x0: decode RC2 {
- 0x0: Jump::c_jr({{
- if (RC1 == 0) {
- return std::make_shared<IllegalInstFault>(
- "source reg x0", machInst);
- }
- NPC = Rc1;
- }}, IsIndirectControl, IsUncondControl, IsCall);
+ 0x0: decode RC1 {
+ 0x1: Jump::c_real_ret({{
+ if (RC1 == 0) {
+ return std::make_shared<IllegalInstFault>(
+ "source reg x0", machInst);
+ }
+ NPC = Rc1;
+ }}, IsIndirectControl, IsUncondControl, IsReturn);
+ default: Jump::c_jr({{
+ if (RC1 == 0) {
+ return std::make_shared<IllegalInstFault>(
+ "source reg x0" ,machInst);
+ }
+ NPC = Rc1;
+ }}, IsIndirectControl, IsUncondControl, IsCall);
+ }
default: CROp::c_mv({{
if (RC1 == 0) {
return std::make_shared<IllegalInstFault>(
@@ -330,14 +339,24 @@
return
std::make_shared<BreakpointFault>(xc->pcState());
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
default: decode RC2 {
- 0x0: Jump::c_jalr({{
- if (RC1 == 0) {
- return std::make_shared<IllegalInstFault>(
- "source reg x0", machInst);
- }
- ra = NPC;
- NPC = Rc1;
- }}, IsIndirectControl, IsUncondControl, IsCall);
+ 0x0: decode RC1 {
+ 0x1: Jump::c_ret({{
+ if (RC1 == 0) {
+ return std::make_shared<IllegalInstFault>(
+ "source reg x0", machInst);
+ }
+ ra = NPC;
+ NPC = Rc1;
+ }}, IsIndirectControl, IsUncondControl, IsReturn);
+ default: Jump::c_jalr({{
+ if (RC1 == 0) {
+ return std::make_shared<IllegalInstFault>(
+ "source reg x0", machInst);
+ }
+ ra = NPC;
+ NPC = Rc1;
+ }}, IsIndirectControl, IsUncondControl, IsCall);
+ }
default: CompressedROp::c_add({{
Rc1_sd = Rc1_sd + Rc2_sd;
}});
@@ -1337,10 +1356,22 @@
}
0x19: decode FUNCT3 {
- 0x0: Jump::jalr({{
- Rd = NPC;
- NPC = (imm + Rs1) & (~0x1);
- }}, IsIndirectControl, IsUncondControl, IsCall);
+ 0x0: decode RS1 {
+ 0x1: decode IMM12 {
+ 0x0: Jump::ret({{
+ Rd = NPC;
+ NPC = (imm + Rs1) & (~0x1);
+ }}, IsIndirectControl, IsUncondControl, IsReturn);
+ default: Jump::ya_jalr({{
+ Rd = NPC;
+ NPC = (imm + Rs1) & (~0x1);
+ }}, IsIndirectControl, IsUncondControl, IsCall);
+ }
+ default: Jump::jalr({{
+ Rd = NPC;
+ NPC = (imm + Rs1) & (~0x1);
+ }}, IsIndirectControl, IsUncondControl, IsCall);
+ }
}
0x1b: JOp::jal({{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I30f4b56fdca760986b503ce9f40d57d703a050a7
Gerrit-Change-Number: 47119
Gerrit-PatchSet: 1
Gerrit-Owner: Guokai Chen <chenguokai...@gmail.com>
Gerrit-MessageType: newchange
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