Nathanael Premillieu has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47042 )
Change subject: cpu-o3: add more DPRINTF for when cache is blocked
......................................................................
cpu-o3: add more DPRINTF for when cache is blocked
Add DPRINTF to track the non execution of memory instructions
when the cache is blocked and their rescheduling when cache
unblocks.
Change-Id: Ieb5eddceaf50ae574ce079e21eb00ac8eaa754ae
---
M src/cpu/o3/inst_queue.cc
M src/cpu/o3/lsq_unit.cc
2 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/src/cpu/o3/inst_queue.cc b/src/cpu/o3/inst_queue.cc
index d736410..cc38104 100644
--- a/src/cpu/o3/inst_queue.cc
+++ b/src/cpu/o3/inst_queue.cc
@@ -1109,11 +1109,16 @@
blocked_inst->clearIssued();
blocked_inst->clearCanIssue();
blockedMemInsts.push_back(blocked_inst);
+ DPRINTF(IQ, "Memory inst [sn:%llu] PC %s is blocked, will be "
+ "reissued later\n", blocked_inst->seqNum,
+ blocked_inst->pcState());
}
void
InstructionQueue::cacheUnblocked()
{
+ DPRINTF(IQ, "Cache is unblocked, rescheduling blocked memory "
+ "instructions\n");
retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts);
// Get the CPU ticking again
cpu->wakeCPU();
diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index a2b1c6d..3393686 100644
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -1247,6 +1247,10 @@
}
state->request()->packetNotSent();
}
+ DPRINTF(LSQUnit, "Memory request (pkt: %s) from inst [sn:%llu] was"
+ " %ssent (cache is blocked: %d, cache_got_blocked: %d)\n",
+ data_pkt->print(), state->inst->seqNum,
+ ret ? "": "not ", lsq->cacheBlocked(), cache_got_blocked);
return ret;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ieb5eddceaf50ae574ce079e21eb00ac8eaa754ae
Gerrit-Change-Number: 47042
Gerrit-PatchSet: 1
Gerrit-Owner: Nathanael Premillieu <nathanael.premill...@huawei.com>
Gerrit-MessageType: newchange
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