Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47304 )
Change subject: arch-arm: Rename debug variables
......................................................................
arch-arm: Rename debug variables
Pave the way for a "debug" namespace.
Change-Id: I1796711cbde527269637b30b0b09cd06c9e25fa1
Signed-off-by: Daniel R. Carvalho <oda...@yahoo.com.br>
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/self_debug.cc
3 files changed, 15 insertions(+), 20 deletions(-)
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index adb1207..d81651b 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1103,16 +1103,16 @@
} else if (stage2) {
tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
tc->setMiscReg(T::HFarIndex, OVAddr);
- } else if (debug > ArmFault::NODEBUG) {
+ } else if (debugType > ArmFault::NODEBUG) {
DBGDS32 Rext = tc->readMiscReg(MISCREG_DBGDSCRext);
tc->setMiscReg(T::FarIndex, faultAddr);
- if (debug == ArmFault::BRKPOINT){
+ if (debugType == ArmFault::BRKPOINT){
Rext.moe = 0x1;
- } else if (debug == ArmFault::VECTORCATCH){
+ } else if (debugType == ArmFault::VECTORCATCH){
Rext.moe = 0x5;
- } else if (debug > ArmFault::VECTORCATCH) {
+ } else if (debugType > ArmFault::VECTORCATCH) {
Rext.moe = 0xa;
- fsr.cm = (debug == ArmFault::WPOINT_CM)? 1 : 0;
+ fsr.cm = (debugType == ArmFault::WPOINT_CM)? 1 : 0;
}
tc->setMiscReg(T::FsrIndex, fsr);
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index da05eb9..6d5411f 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -456,7 +456,7 @@
bool stage2;
bool s1ptw;
ArmFault::TranMethod tranMethod;
- ArmFault::DebugType debug;
+ ArmFault::DebugType debugType;
public:
AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain,
@@ -465,7 +465,8 @@
ArmFault::DebugType _debug = ArmFault::NODEBUG) :
faultAddr(_faultAddr), OVAddr(0), write(_write),
domain(_domain), source(_source), srcEncoded(0),
- stage2(_stage2), s1ptw(false), tranMethod(_tranMethod),
debug(_debug)
+ stage2(_stage2), s1ptw(false), tranMethod(_tranMethod),
+ debugType(_debug)
{}
bool getFaultVAddr(Addr &va) const override;
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index 21d4000..13ee2f7 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -96,8 +96,7 @@
if (p.enable && p.isActive(pc) &&(!to32 || !p.onUse)) {
const DBGBCR ctr = p.getControlReg(tc);
if (p.isEnabled(tc, el, ctr.hmc, ctr.ssc, ctr.pmc)) {
- bool debug = p.test(tc, pc, el, ctr, false);
- if (debug){
+ if (p.test(tc, pc, el, ctr, false)) {
if (to32)
p.onUse = true;
return triggerException(tc, pc);
@@ -138,8 +137,7 @@
for (auto &p: arWatchPoints){
idxtmp ++;
if (p.enable) {
- bool debug = p.test(tc, vaddr, el, write, atomic, size);
- if (debug){
+ if (p.test(tc, vaddr, el, write, atomic, size)) {
return triggerWatchpointException(tc, vaddr, write, cm);
}
}
@@ -212,12 +210,8 @@
bool
BrkPoint::testLinkedBk(ThreadContext *tc, Addr vaddr, ExceptionLevel el)
{
- bool debug = false;
const DBGBCR ctr = getControlReg(tc);
- if ((ctr.bt & 0x1) && enable) {
- debug = test(tc, vaddr, el, ctr, true);
- }
- return debug;
+ return ((ctr.bt & 0x1) && enable) && test(tc, vaddr, el, ctr, true);
}
bool
@@ -730,12 +724,12 @@
return NoFault;
ExceptionLevel el = (ExceptionLevel) currEL(tc);
- bool debug;
+ bool do_debug;
if (fault == nullptr)
- debug = vcExcpt->addressMatching(tc, addr, el);
+ do_debug = vcExcpt->addressMatching(tc, addr, el);
else
- debug = vcExcpt->exceptionTrapping(tc, el, fault);
- if (debug) {
+ do_debug = vcExcpt->exceptionTrapping(tc, el, fault);
+ if (do_debug) {
if (enableTdeTge) {
return std::make_shared<HypervisorTrap>(0, 0x22,
EC_PREFETCH_ABORT_TO_HYP);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1796711cbde527269637b30b0b09cd06c9e25fa1
Gerrit-Change-Number: 47304
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-MessageType: newchange
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