Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47309 )
Change subject: mem: Adopt a memory namespace for memories
......................................................................
mem: Adopt a memory namespace for memories
Encapsulate every class inheriting from Abstract or Physical
memories, and the memory controller in a memory namespace.
Change-Id: I228f7e55efc395089e3616ae0a0a6325867bd782
Issued-on: https://gem5.atlassian.net/browse/GEM5-983
Signed-off-by: Daniel R. Carvalho <oda...@yahoo.com.br>
---
M src/arch/arm/semihosting.cc
M src/cpu/kvm/vm.cc
M src/cpu/o3/inst_queue.hh
M src/mem/AbstractMemory.py
M src/mem/CfiMemory.py
M src/mem/DRAMInterface.py
M src/mem/DRAMSim2.py
M src/mem/DRAMsim3.py
M src/mem/MemCtrl.py
M src/mem/MemInterface.py
M src/mem/NVMInterface.py
M src/mem/SimpleMemory.py
M src/mem/abstract_mem.cc
M src/mem/abstract_mem.hh
M src/mem/cfi_mem.cc
M src/mem/cfi_mem.hh
M src/mem/dramsim2.cc
M src/mem/dramsim2.hh
M src/mem/dramsim2_wrapper.cc
M src/mem/dramsim2_wrapper.hh
M src/mem/dramsim3.cc
M src/mem/dramsim3.hh
M src/mem/dramsim3_wrapper.cc
M src/mem/dramsim3_wrapper.hh
M src/mem/mem_ctrl.cc
M src/mem/mem_ctrl.hh
M src/mem/mem_interface.cc
M src/mem/mem_interface.hh
M src/mem/physical.cc
M src/mem/physical.hh
M src/mem/ruby/system/RubySystem.hh
M src/mem/simple_mem.cc
M src/mem/simple_mem.hh
M src/sim/system.cc
M src/sim/system.hh
35 files changed, 115 insertions(+), 24 deletions(-)
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 1f06b51..59ea4aa 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -551,7 +551,7 @@
Addr &heap_base, Addr &heap_limit,
Addr &stack_base, Addr &stack_limit)
{
- const PhysicalMemory &phys = tc->getSystemPtr()->getPhysMem();
+ const memory::PhysicalMemory &phys = tc->getSystemPtr()->getPhysMem();
const AddrRangeList memories = phys.getConfAddrRanges();
fatal_if(memories.size() < 1, "No memories reported from System");
warn_if(memories.size() > 1, "Multiple physical memory ranges
available. "
diff --git a/src/cpu/kvm/vm.cc b/src/cpu/kvm/vm.cc
index f1fdeec..cd975ac 100644
--- a/src/cpu/kvm/vm.cc
+++ b/src/cpu/kvm/vm.cc
@@ -50,6 +50,7 @@
#include "cpu/kvm/base.hh"
#include "debug/Kvm.hh"
+#include "mem/physical.hh"
#include "params/KvmVM.hh"
#include "sim/system.hh"
@@ -355,7 +356,7 @@
KvmVM::delayedStartup()
{
assert(system); // set by the system during its construction
- const std::vector<BackingStoreEntry> &memories(
+ const std::vector<memory::BackingStoreEntry> &memories(
system->getPhysMem().getBackingStore());
DPRINTF(Kvm, "Mapping %i memory region(s)\n", memories.size());
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index b69344a..b2d9303 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -65,7 +65,11 @@
{
struct O3CPUParams;
+
+namespace memory
+{
class MemInterface;
+} // namespace memory
namespace o3
{
@@ -284,7 +288,7 @@
CPU *cpu;
/** Cache interface. */
- MemInterface *dcacheInterface;
+ memory::MemInterface *dcacheInterface;
/** Pointer to IEW stage. */
IEW *iewStage;
diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py
index 3fe94f3..ed2a02c 100644
--- a/src/mem/AbstractMemory.py
+++ b/src/mem/AbstractMemory.py
@@ -43,7 +43,7 @@
type = 'AbstractMemory'
abstract = True
cxx_header = "mem/abstract_mem.hh"
- cxx_class = 'gem5::AbstractMemory'
+ cxx_class = 'gem5::memory::AbstractMemory'
# A default memory size of 128 MiB (starting at 0) is used to
# simplify the regressions
diff --git a/src/mem/CfiMemory.py b/src/mem/CfiMemory.py
index 6ac539e..aa6b18a 100644
--- a/src/mem/CfiMemory.py
+++ b/src/mem/CfiMemory.py
@@ -43,7 +43,7 @@
class CfiMemory(AbstractMemory):
type = 'CfiMemory'
cxx_header = "mem/cfi_mem.hh"
- cxx_class = 'gem5::CfiMemory'
+ cxx_class = 'gem5::memory::CfiMemory'
port = ResponsePort("Response port")
diff --git a/src/mem/DRAMInterface.py b/src/mem/DRAMInterface.py
index 91e1540..3f938dd 100644
--- a/src/mem/DRAMInterface.py
+++ b/src/mem/DRAMInterface.py
@@ -49,7 +49,7 @@
class DRAMInterface(MemInterface):
type = 'DRAMInterface'
cxx_header = "mem/mem_interface.hh"
- cxx_class = 'gem5::DRAMInterface'
+ cxx_class = 'gem5::memory::DRAMInterface'
# scheduler page policy
page_policy = Param.PageManage('open_adaptive', "Page management
policy")
diff --git a/src/mem/DRAMSim2.py b/src/mem/DRAMSim2.py
index d6f92ef..11f9b4e 100644
--- a/src/mem/DRAMSim2.py
+++ b/src/mem/DRAMSim2.py
@@ -40,7 +40,7 @@
class DRAMSim2(AbstractMemory):
type = 'DRAMSim2'
cxx_header = "mem/dramsim2.hh"
- cxx_class = 'gem5::DRAMSim2'
+ cxx_class = 'gem5::memory::DRAMSim2'
# A single port for now
port = ResponsePort("This port sends responses and receives requests")
diff --git a/src/mem/DRAMsim3.py b/src/mem/DRAMsim3.py
index 65cd0ba..01a735e 100644
--- a/src/mem/DRAMsim3.py
+++ b/src/mem/DRAMsim3.py
@@ -40,7 +40,7 @@
class DRAMsim3(AbstractMemory):
type = 'DRAMsim3'
cxx_header = "mem/dramsim3.hh"
- cxx_class = 'gem5::DRAMsim3'
+ cxx_class = 'gem5::memory::DRAMsim3'
# A single port for now
port = ResponsePort("port for receiving requests from"
diff --git a/src/mem/MemCtrl.py b/src/mem/MemCtrl.py
index 5e559da..90d0e50 100644
--- a/src/mem/MemCtrl.py
+++ b/src/mem/MemCtrl.py
@@ -53,7 +53,7 @@
class MemCtrl(QoSMemCtrl):
type = 'MemCtrl'
cxx_header = "mem/mem_ctrl.hh"
- cxx_class = 'gem5::MemCtrl'
+ cxx_class = 'gem5::memory::MemCtrl'
# single-ported on the system interface side, instantiate with a
# bus in front of the controller for multiple ports
diff --git a/src/mem/MemInterface.py b/src/mem/MemInterface.py
index 720b66b..10eb430 100644
--- a/src/mem/MemInterface.py
+++ b/src/mem/MemInterface.py
@@ -55,7 +55,7 @@
type = 'MemInterface'
abstract = True
cxx_header = "mem/mem_interface.hh"
- cxx_class = 'gem5::MemInterface'
+ cxx_class = 'gem5::memory::MemInterface'
# Allow the interface to set required controller buffer sizes
# each entry corresponds to a burst for the specific memory channel
diff --git a/src/mem/NVMInterface.py b/src/mem/NVMInterface.py
index 9c4ec8b..5c8b27b 100644
--- a/src/mem/NVMInterface.py
+++ b/src/mem/NVMInterface.py
@@ -44,7 +44,7 @@
class NVMInterface(MemInterface):
type = 'NVMInterface'
cxx_header = "mem/mem_interface.hh"
- cxx_class = 'gem5::NVMInterface'
+ cxx_class = 'gem5::memory::NVMInterface'
# NVM DIMM could have write buffer to offload writes
# define buffer depth, which will limit the number of pending writes
diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py
index c1e0c27..1d1457e 100644
--- a/src/mem/SimpleMemory.py
+++ b/src/mem/SimpleMemory.py
@@ -42,7 +42,7 @@
class SimpleMemory(AbstractMemory):
type = 'SimpleMemory'
cxx_header = "mem/simple_mem.hh"
- cxx_class = 'gem5::SimpleMemory'
+ cxx_class = 'gem5::memory::SimpleMemory'
port = ResponsePort("This port sends responses and receives requests")
latency = Param.Latency('30ns', "Request to response latency")
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index 902af59..a110a1e 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -54,6 +54,9 @@
namespace gem5
{
+namespace memory
+{
+
AbstractMemory::AbstractMemory(const Params &p) :
ClockedObject(p), range(p.range), pmemAddr(NULL),
backdoor(params().range, nullptr,
@@ -509,4 +512,5 @@
}
}
+} // namespace memory
} // namespace gem5
diff --git a/src/mem/abstract_mem.hh b/src/mem/abstract_mem.hh
index 2f3a980..53b7940 100644
--- a/src/mem/abstract_mem.hh
+++ b/src/mem/abstract_mem.hh
@@ -57,6 +57,9 @@
class System;
+namespace memory
+{
+
/**
* Locked address class that represents a physical address and a
* context id.
@@ -348,6 +351,7 @@
void functionalAccess(PacketPtr pkt);
};
+} // namespace memory
} // namespace gem5
#endif //__MEM_ABSTRACT_MEMORY_HH__
diff --git a/src/mem/cfi_mem.cc b/src/mem/cfi_mem.cc
index 22face1..9075d14 100644
--- a/src/mem/cfi_mem.cc
+++ b/src/mem/cfi_mem.cc
@@ -51,6 +51,9 @@
namespace gem5
{
+namespace memory
+{
+
bool
CfiMemory::BlockData::isLocked(Addr block_address) const
{
@@ -732,4 +735,5 @@
std::memset(host_address, 0xff, blockSize);
}
+} // namespace memory
} // namespace gem5
diff --git a/src/mem/cfi_mem.hh b/src/mem/cfi_mem.hh
index 89998b8..76278f6 100644
--- a/src/mem/cfi_mem.hh
+++ b/src/mem/cfi_mem.hh
@@ -47,6 +47,9 @@
namespace gem5
{
+namespace memory
+{
+
/**
* CfiMemory: This is modelling a flash memory adhering to the
* Common Flash Interface (CFI):
@@ -395,6 +398,7 @@
uint64_t cfiQuery(Addr addr);
};
+} // namespace memory
} // namespace gem5
#endif
diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc
index aac4aea..028ed43 100644
--- a/src/mem/dramsim2.cc
+++ b/src/mem/dramsim2.cc
@@ -47,6 +47,9 @@
namespace gem5
{
+namespace memory
+{
+
DRAMSim2::DRAMSim2(const Params &p) :
AbstractMemory(p),
port(name() + ".port", *this),
@@ -392,4 +395,5 @@
mem.recvRespRetry();
}
+} // namespace memory
} // namespace gem5
diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh
index ca55dea..1fc5b64 100644
--- a/src/mem/dramsim2.hh
+++ b/src/mem/dramsim2.hh
@@ -53,6 +53,9 @@
namespace gem5
{
+namespace memory
+{
+
class DRAMSim2 : public AbstractMemory
{
private:
@@ -207,6 +210,7 @@
};
+} // namespace memory
} // namespace gem5
#endif // __MEM_DRAMSIM2_HH__
diff --git a/src/mem/dramsim2_wrapper.cc b/src/mem/dramsim2_wrapper.cc
index 7ea0de6..4a16112 100644
--- a/src/mem/dramsim2_wrapper.cc
+++ b/src/mem/dramsim2_wrapper.cc
@@ -57,6 +57,9 @@
namespace gem5
{
+namespace memory
+{
+
/**
* DRAMSim2 requires SHOW_SIM_OUTPUT to be defined (declared extern in
* the DRAMSim2 print macros), otherwise we get linking errors due to
@@ -200,4 +203,5 @@
dramsim->update();
}
+} // namespace memory
} // namespace gem5
diff --git a/src/mem/dramsim2_wrapper.hh b/src/mem/dramsim2_wrapper.hh
index f96a78b..456f03f 100644
--- a/src/mem/dramsim2_wrapper.hh
+++ b/src/mem/dramsim2_wrapper.hh
@@ -59,6 +59,9 @@
namespace gem5
{
+namespace memory
+{
+
/**
* Wrapper class to avoid having DRAMSim2 names like ClockDomain etc
* clashing with the normal gem5 world. Many of the DRAMSim2 headers
@@ -161,6 +164,7 @@
void tick();
};
+} // namespace memory
} // namespace gem5
#endif //__MEM_DRAMSIM2_WRAPPER_HH__
diff --git a/src/mem/dramsim3.cc b/src/mem/dramsim3.cc
index 172b5d0..fbffc7b 100644
--- a/src/mem/dramsim3.cc
+++ b/src/mem/dramsim3.cc
@@ -46,6 +46,9 @@
namespace gem5
{
+namespace memory
+{
+
DRAMsim3::DRAMsim3(const Params &p) :
AbstractMemory(p),
port(name() + ".port", *this),
@@ -390,4 +393,5 @@
mem.recvRespRetry();
}
+} // namespace memory
} // namespace gem5
diff --git a/src/mem/dramsim3.hh b/src/mem/dramsim3.hh
index 43e34e4..f8fd54a 100644
--- a/src/mem/dramsim3.hh
+++ b/src/mem/dramsim3.hh
@@ -55,6 +55,9 @@
namespace gem5
{
+namespace memory
+{
+
class DRAMsim3 : public AbstractMemory
{
private:
@@ -218,6 +221,7 @@
};
+} // namespace memory
} // namespace gem5
#endif // __MEM_DRAMSIM3_HH__
diff --git a/src/mem/dramsim3_wrapper.cc b/src/mem/dramsim3_wrapper.cc
index 703a1eb..8d22ff3 100644
--- a/src/mem/dramsim3_wrapper.cc
+++ b/src/mem/dramsim3_wrapper.cc
@@ -58,6 +58,9 @@
namespace gem5
{
+namespace memory
+{
+
DRAMsim3Wrapper::DRAMsim3Wrapper(const std::string& config_file,
const std::string& working_dir,
std::function<void(uint64_t)> read_cb,
@@ -154,4 +157,5 @@
dramsim->ClockTick();
}
+} // namespace memory
} // namespace gem5
diff --git a/src/mem/dramsim3_wrapper.hh b/src/mem/dramsim3_wrapper.hh
index 45276c9..41b1088 100644
--- a/src/mem/dramsim3_wrapper.hh
+++ b/src/mem/dramsim3_wrapper.hh
@@ -59,6 +59,9 @@
namespace gem5
{
+namespace memory
+{
+
/**
* Wrapper class to avoid having DRAMsim3 names like ClockDomain etc
* clashing with the normal gem5 world. Many of the DRAMsim3 headers
@@ -160,6 +163,7 @@
void tick();
};
+} // namespace memory
} // namespace gem5
#endif //__MEM_DRAMSIM3_WRAPPER_HH__
diff --git a/src/mem/mem_ctrl.cc b/src/mem/mem_ctrl.cc
index 0e1c0a6..9d9c4eb 100644
--- a/src/mem/mem_ctrl.cc
+++ b/src/mem/mem_ctrl.cc
@@ -52,8 +52,11 @@
namespace gem5
{
+namespace memory
+{
+
MemCtrl::MemCtrl(const MemCtrlParams &p) :
- memory::qos::MemCtrl(p),
+ qos::MemCtrl(p),
port(name() + ".port", *this), isTimingMode(false),
retryRdReq(false), retryWrReq(false),
nextReqEvent([this]{ processNextReqEvent(); }, name()),
@@ -1395,7 +1398,7 @@
MemCtrl::getPort(const std::string &if_name, PortID idx)
{
if (if_name != "port") {
- return memory::qos::MemCtrl::getPort(if_name, idx);
+ return qos::MemCtrl::getPort(if_name, idx);
} else {
return port;
}
@@ -1513,4 +1516,5 @@
return ctrl.recvTimingReq(pkt);
}
+} // namespace memory
} // namespace gem5
diff --git a/src/mem/mem_ctrl.hh b/src/mem/mem_ctrl.hh
index a30fcb3..4eef268 100644
--- a/src/mem/mem_ctrl.hh
+++ b/src/mem/mem_ctrl.hh
@@ -63,6 +63,9 @@
namespace gem5
{
+namespace memory
+{
+
class DRAMInterface;
class NVMInterface;
@@ -236,7 +239,7 @@
* please cite the paper.
*
*/
-class MemCtrl : public memory::qos::MemCtrl
+class MemCtrl : public qos::MemCtrl
{
private:
@@ -712,6 +715,7 @@
};
+} // namespace memory
} // namespace gem5
#endif //__MEM_CTRL_HH__
diff --git a/src/mem/mem_interface.cc b/src/mem/mem_interface.cc
index e9c35d2..8b98403 100644
--- a/src/mem/mem_interface.cc
+++ b/src/mem/mem_interface.cc
@@ -54,6 +54,9 @@
using namespace Data;
+namespace memory
+{
+
MemInterface::MemInterface(const MemInterfaceParams &_p)
: AbstractMemory(_p),
addrMapping(_p.addr_mapping),
@@ -2624,4 +2627,5 @@
busUtilWrite = avgWrBW / peakBW * 100;
}
+} // namespace memory
} // namespace gem5
diff --git a/src/mem/mem_interface.hh b/src/mem/mem_interface.hh
index 03e5582..a71f84f 100644
--- a/src/mem/mem_interface.hh
+++ b/src/mem/mem_interface.hh
@@ -67,6 +67,9 @@
namespace gem5
{
+namespace memory
+{
+
/**
* General interface to memory device
* Includes functions and parameters shared across media types
@@ -1263,6 +1266,7 @@
NVMInterface(const NVMInterfaceParams &_p);
};
+} // namespace memory
} // namespace gem5
#endif //__MEM_INTERFACE_HH__
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index bd7b2de..ae20fb6 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -71,6 +71,9 @@
namespace gem5
{
+namespace memory
+{
+
PhysicalMemory::PhysicalMemory(const std::string& _name,
const std::vector<AbstractMemory*>&
_memories,
bool mmap_using_noreserve,
@@ -471,4 +474,5 @@
filename);
}
+} // namespace memory
} // namespace gem5
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 6a39e01..b7ec8eb 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -50,6 +50,9 @@
namespace gem5
{
+namespace memory
+{
+
/**
* Forward declaration to avoid header dependencies.
*/
@@ -277,6 +280,7 @@
};
+} // namespace memory
} // namespace gem5
#endif //__MEM_PHYSICAL_HH__
diff --git a/src/mem/ruby/system/RubySystem.hh
b/src/mem/ruby/system/RubySystem.hh
index 36c271a..e16d699 100644
--- a/src/mem/ruby/system/RubySystem.hh
+++ b/src/mem/ruby/system/RubySystem.hh
@@ -49,6 +49,11 @@
namespace gem5
{
+namespace memory
+{
+class SimpleMemory;
+} // namespace memory
+
namespace ruby
{
@@ -70,7 +75,7 @@
static bool getWarmupEnabled() { return m_warmup_enabled; }
static bool getCooldownEnabled() { return m_cooldown_enabled; }
- SimpleMemory *getPhysMem() { return m_phys_mem; }
+ memory::SimpleMemory *getPhysMem() { return m_phys_mem; }
Cycles getStartCycle() { return m_start_cycle; }
bool getAccessBackingStore() { return m_access_backing_store; }
@@ -137,7 +142,7 @@
static bool m_warmup_enabled;
static unsigned m_systems_to_warmup;
static bool m_cooldown_enabled;
- SimpleMemory *m_phys_mem;
+ memory::SimpleMemory *m_phys_mem;
const bool m_access_backing_store;
//std::vector<Network *> m_networks;
diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
index ec46702..ced3a38 100644
--- a/src/mem/simple_mem.cc
+++ b/src/mem/simple_mem.cc
@@ -47,6 +47,9 @@
namespace gem5
{
+namespace memory
+{
+
SimpleMemory::SimpleMemory(const SimpleMemoryParams &p) :
AbstractMemory(p),
port(name() + ".port", *this), latency(p.latency),
@@ -303,4 +306,5 @@
mem.recvRespRetry();
}
+} // namespace memory
} // namespace gem5
diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh
index 153ea10..fc6d684 100644
--- a/src/mem/simple_mem.hh
+++ b/src/mem/simple_mem.hh
@@ -55,6 +55,9 @@
namespace gem5
{
+namespace memory
+{
+
/**
* The simple memory is a basic single-ported memory controller with
* a configurable throughput and latency.
@@ -192,6 +195,7 @@
void recvRespRetry();
};
+} // namespace memory
} // namespace gem5
#endif //__MEM_SIMPLE_MEMORY_HH__
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 4619de9..301ebfb 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -379,7 +379,8 @@
}
void
-System::addDeviceMemory(RequestorID requestor_id, AbstractMemory
*deviceMemory)
+System::addDeviceMemory(RequestorID requestor_id,
+ memory::AbstractMemory *deviceMemory)
{
deviceMemMap[requestor_id].push_back(deviceMemory);
}
@@ -394,7 +395,7 @@
return (getDeviceMemory(pkt) != nullptr);
}
-AbstractMemory *
+memory::AbstractMemory *
System::getDeviceMemory(const PacketPtr& pkt) const
{
const RequestorID& rid = pkt->requestorId();
diff --git a/src/sim/system.hh b/src/sim/system.hh
index e5215a6..8194138 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -111,7 +111,7 @@
SystemPort _systemPort;
// Map of memory address ranges for devices with their own backing
stores
- std::unordered_map<RequestorID, std::vector<AbstractMemory *>>
+ std::unordered_map<RequestorID, std::vector<memory::AbstractMemory *>>
deviceMemMap;
public:
@@ -345,7 +345,7 @@
bool validKvmEnvironment() const;
/** Get a pointer to access the physical memory of the system */
- PhysicalMemory& getPhysMem() { return physmem; }
+ memory::PhysicalMemory& getPhysMem() { return physmem; }
/** Amount of physical memory that is still free */
Addr freeMemSize(int poolID = 0) const;
@@ -368,7 +368,7 @@
* and range match something in the device memory map.
*/
void addDeviceMemory(RequestorID requestorId,
- AbstractMemory *deviceMemory);
+ memory::AbstractMemory *deviceMemory);
/**
* Similar to isMemAddr but for devices. Checks if a physical address
@@ -380,7 +380,7 @@
/**
* Return a pointer to the device memory.
*/
- AbstractMemory *getDeviceMemory(const PacketPtr& pkt) const;
+ memory::AbstractMemory *getDeviceMemory(const PacketPtr& pkt) const;
/*
* Return the list of address ranges backed by a shadowed ROM.
@@ -422,7 +422,7 @@
KvmVM *const kvmVM = nullptr;
- PhysicalMemory physmem;
+ memory::PhysicalMemory physmem;
AddrRangeList ShadowRomRanges;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I228f7e55efc395089e3616ae0a0a6325867bd782
Gerrit-Change-Number: 47309
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-MessageType: newchange
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