Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27587 )
Change subject: cpu: Check for instruction-count events before fetch
......................................................................
cpu: Check for instruction-count events before fetch
Instruction fetch should not commence if there already is an
instruction-count event in the queue.
The most conspicuous scenario where this leads to obvious breakage,
is guest debugging. Imagine the first bytes in the program pointed to
by _start are invalid instruction encoding, and we pass the --wait-gdb
flag. Then in GDB we set $pc to point to valid instructions, and we
"continue". gem5 will abort with "invalid instruction".
This is not how real targets behave: neither software- (e.g. ptrace)
based debuggers, nor low-level (e.g. OpenOCD or XMD connected over
JTAG to debug early initialization code eg when the MMU has not been
switched on yet, etc.) Fetching should start from where $pc was set
to. This patch tries to model this behavior.
Change-Id: Ibce6fdbbb082edf1073ae96745bc7867878f99ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27587
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
Maintainer: Jason Lowe-Power <power...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/cpu/simple/atomic.cc
M src/cpu/simple/base.cc
M src/cpu/simple/base.hh
M src/cpu/simple/timing.cc
4 files changed, 11 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 4b9b773..12accc3 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -646,6 +646,8 @@
return;
}
+ serviceInstCountEvents();
+
Fault fault = NoFault;
TheISA::PCState pcState = thread->pcState();
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 0a4595c..135094f 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -302,6 +302,12 @@
instRequestorId(), instAddr);
}
+void
+BaseSimpleCPU::serviceInstCountEvents()
+{
+ SimpleExecContext &t_info = *threadInfo[curThread];
+ t_info.thread->comInstEventQueue.serviceEvents(t_info.numInst);
+}
void
BaseSimpleCPU::preExecute()
@@ -316,9 +322,6 @@
t_info.setPredicate(true);
t_info.setMemAccPredicate(true);
- // check for instruction-count-based events
- thread->comInstEventQueue.serviceEvents(t_info.numInst);
-
// decode the instruction
TheISA::PCState pcState = thread->pcState();
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 8117138..cee786d 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -130,6 +130,7 @@
public:
void checkForInterrupts();
void setupFetchRequest(const RequestPtr &req);
+ void serviceInstCountEvents();
void preExecute();
void postExecute();
void advancePC(const Fault &fault);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index ad0e039..76bc1af 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -805,6 +805,8 @@
if (tryCompleteDrain())
return;
+ serviceInstCountEvents();
+
if (_status == BaseSimpleCPU::Running) {
// kick off fetch of next instruction... callback from icache
// response will cause that instruction to be executed,
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibce6fdbbb082edf1073ae96745bc7867878f99ca
Gerrit-Change-Number: 27587
Gerrit-PatchSet: 4
Gerrit-Owner: Boris Shingarov <shinga...@labware.com>
Gerrit-Reviewer: Boris Shingarov <shinga...@labware.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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