Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48142 )
Change subject: arch: Add TypeTLB Param in BaseTLB
......................................................................
arch: Add TypeTLB Param in BaseTLB
This patch is adding an enum Param in the BaseTLB to tag which kind of
translation entries the TLB is holding
* instruction: holding instruction entries
* data: holding data entries
* unified: holding instruction and data entries
JIRA: https://gem5.atlassian.net/browse/GEM5-790
Change-Id: I033f840652f354523f48e9eb78033ea759b5d0e0
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/ArmMMU.py
M src/arch/arm/ArmTLB.py
M src/arch/arm/fastmodel/iris/Iris.py
M src/arch/generic/BaseTLB.py
M src/arch/generic/tlb.hh
M src/arch/mips/MipsMMU.py
M src/arch/power/PowerMMU.py
M src/arch/riscv/RiscvMMU.py
M src/arch/sparc/SparcMMU.py
M src/arch/x86/X86MMU.py
10 files changed, 43 insertions(+), 17 deletions(-)
diff --git a/src/arch/arm/ArmMMU.py b/src/arch/arm/ArmMMU.py
index d7ed550..5017fa8 100644
--- a/src/arch/arm/ArmMMU.py
+++ b/src/arch/arm/ArmMMU.py
@@ -70,8 +70,12 @@
PyBindMethod('wireComponents'),
]
- stage2_itb = Param.ArmTLB(ArmStage2TLB(), "Stage 2 Instruction TLB")
- stage2_dtb = Param.ArmTLB(ArmStage2TLB(), "Stage 2 Data TLB")
+ stage2_itb = Param.ArmTLB(
+ ArmStage2TLB(entry_type="instruction"),
+ "Stage 2 Instruction TLB")
+ stage2_dtb = Param.ArmTLB(
+ ArmStage2TLB(entry_type="data"),
+ "Stage 2 Data TLB")
itb_walker = Param.ArmTableWalker(
ArmTableWalker(), "HW Table walker")
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index 4681d2e..5c4cca0 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -53,7 +53,7 @@
is_stage2 = True
class ArmITB(ArmTLB):
- pass
+ entry_type = "instruction"
class ArmDTB(ArmTLB):
- pass
+ entry_type = "data"
diff --git a/src/arch/arm/fastmodel/iris/Iris.py
b/src/arch/arm/fastmodel/iris/Iris.py
index 4bc6add..4979715 100644
--- a/src/arch/arm/fastmodel/iris/Iris.py
+++ b/src/arch/arm/fastmodel/iris/Iris.py
@@ -53,8 +53,8 @@
type = 'IrisMMU'
cxx_class = 'gem5::Iris::MMU'
cxx_header = 'arch/arm/fastmodel/iris/mmu.hh'
- itb = IrisTLB()
- dtb = IrisTLB()
+ itb = IrisTLB(entry_type="instruction")
+ dtb = IrisTLB(entry_type="data")
class IrisInterrupts(BaseInterrupts):
type = 'IrisInterrupts'
diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py
index a090a06..4fe2338 100644
--- a/src/arch/generic/BaseTLB.py
+++ b/src/arch/generic/BaseTLB.py
@@ -28,6 +28,18 @@
from m5.params import *
from m5.SimObject import SimObject
+class TypeTLB(ScopedEnum):
+ """
+ instruction: TLB contains instruction entries only
+ data: TLB contains data entries only
+ unified: TLB contains both instruction and data entries
+ """
+ map = {
+ 'instruction' : 0x1,
+ 'data' : 0x2,
+ 'unified' : 0x3,
+ }
+
class BaseTLB(SimObject):
type = 'BaseTLB'
abstract = True
@@ -41,3 +53,5 @@
mem_side_port = RequestPort("Port closer to memory side")
master = DeprecatedParam(mem_side_port,
'`master` is now called `mem_side_port`')
+
+ entry_type = Param.TypeTLB("Instruction/Data/Unified TLB entries")
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index ac05726..7e2ef44 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -43,7 +43,9 @@
#include "arch/generic/mmu.hh"
#include "base/logging.hh"
+#include "enums/TypeTLB.hh"
#include "mem/request.hh"
+#include "params/BaseTLB.hh"
#include "sim/sim_object.hh"
namespace gem5
@@ -54,7 +56,11 @@
class BaseTLB : public SimObject
{
protected:
- BaseTLB(const Params &p) : SimObject(p) {}
+ BaseTLB(const BaseTLBParams &p)
+ : SimObject(p), _type(p.entry_type)
+ {}
+
+ TypeTLB _type;
public:
virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
@@ -111,6 +117,8 @@
virtual Port* getTableWalkerPort() { return NULL; }
void memInvalidate() { flushAll(); }
+
+ TypeTLB type() const { return _type; }
};
} // namespace gem5
diff --git a/src/arch/mips/MipsMMU.py b/src/arch/mips/MipsMMU.py
index 0de1002..ccaae24 100644
--- a/src/arch/mips/MipsMMU.py
+++ b/src/arch/mips/MipsMMU.py
@@ -42,5 +42,5 @@
type = 'MipsMMU'
cxx_class = 'gem5::MipsISA::MMU'
cxx_header = 'arch/mips/mmu.hh'
- itb = MipsTLB()
- dtb = MipsTLB()
+ itb = MipsTLB(entry_type="instruction")
+ dtb = MipsTLB(entry_type="data")
diff --git a/src/arch/power/PowerMMU.py b/src/arch/power/PowerMMU.py
index db9673d..aaf288a 100644
--- a/src/arch/power/PowerMMU.py
+++ b/src/arch/power/PowerMMU.py
@@ -42,5 +42,5 @@
type = 'PowerMMU'
cxx_class = 'gem5::PowerISA::MMU'
cxx_header = 'arch/power/mmu.hh'
- itb = PowerTLB()
- dtb = PowerTLB()
+ itb = PowerTLB(entry_type="instruction")
+ dtb = PowerTLB(entry_type="data")
diff --git a/src/arch/riscv/RiscvMMU.py b/src/arch/riscv/RiscvMMU.py
index 78fa7f5..193398c 100644
--- a/src/arch/riscv/RiscvMMU.py
+++ b/src/arch/riscv/RiscvMMU.py
@@ -47,8 +47,8 @@
cxx_class = 'gem5::RiscvISA::MMU'
cxx_header = 'arch/riscv/mmu.hh'
- itb = RiscvTLB()
- dtb = RiscvTLB()
+ itb = RiscvTLB(entry_type="instruction")
+ dtb = RiscvTLB(entry_type="data")
pma_checker = Param.PMAChecker(PMAChecker(), "PMA Checker")
pmp = Param.PMP(PMP(), "Physical Memory Protection Unit")
diff --git a/src/arch/sparc/SparcMMU.py b/src/arch/sparc/SparcMMU.py
index 72aea5f..671ece6 100644
--- a/src/arch/sparc/SparcMMU.py
+++ b/src/arch/sparc/SparcMMU.py
@@ -44,5 +44,5 @@
type = 'SparcMMU'
cxx_class = 'gem5::SparcISA::MMU'
cxx_header = 'arch/sparc/mmu.hh'
- itb = SparcTLB()
- dtb = SparcTLB()
+ itb = SparcTLB(entry_type="instruction")
+ dtb = SparcTLB(entry_type="data")
diff --git a/src/arch/x86/X86MMU.py b/src/arch/x86/X86MMU.py
index bc24d9a..cbee8a3 100644
--- a/src/arch/x86/X86MMU.py
+++ b/src/arch/x86/X86MMU.py
@@ -42,8 +42,8 @@
type = 'X86MMU'
cxx_class = 'gem5::X86ISA::MMU'
cxx_header = 'arch/x86/mmu.hh'
- itb = X86TLB()
- dtb = X86TLB()
+ itb = X86TLB(entry_type="instruction")
+ dtb = X86TLB(entry_type="data")
@classmethod
def walkerPorts(cls):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I033f840652f354523f48e9eb78033ea759b5d0e0
Gerrit-Change-Number: 48142
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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