Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48143 )
Change subject: arch-arm, configs: Remove ArmITB/ArmDTB
......................................................................
arch-arm, configs: Remove ArmITB/ArmDTB
Removing ArmITB and ArmDTB makes sense as it implies a fixed 2 TLBs
system; by using the generic ArmTLB class we open up to a more generic
configuration
This is also aligning to the other ISAs
Change-Id: Ifc5cf7c41484d4f45b14d1766833ad4c4f7e9e86
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M configs/common/cores/arm/HPI.py
M src/arch/arm/ArmMMU.py
M src/arch/arm/ArmTLB.py
3 files changed, 6 insertions(+), 17 deletions(-)
diff --git a/configs/common/cores/arm/HPI.py
b/configs/common/cores/arm/HPI.py
index 68b3862..624c40c 100644
--- a/configs/common/cores/arm/HPI.py
+++ b/configs/common/cores/arm/HPI.py
@@ -1328,15 +1328,9 @@
HPI_MiscFU() # 6
]
-class HPI_DTB(ArmDTB):
- size = 256
-
-class HPI_ITB(ArmITB):
- size = 256
-
class HPI_MMU(ArmMMU):
- itb = HPI_ITB()
- dtb = HPI_DTB()
+ itb = ArmTLB(entry_type="instruction", size=256)
+ dtb = ArmTLB(entry_type="data", size=256)
class HPI_WalkCache(Cache):
data_latency = 4
diff --git a/src/arch/arm/ArmMMU.py b/src/arch/arm/ArmMMU.py
index 5017fa8..1596574 100644
--- a/src/arch/arm/ArmMMU.py
+++ b/src/arch/arm/ArmMMU.py
@@ -35,7 +35,7 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from m5.objects.ArmTLB import ArmITB, ArmDTB, ArmStage2TLB
+from m5.objects.ArmTLB import ArmTLB, ArmStage2TLB
from m5.objects.BaseMMU import BaseMMU
from m5.objects.ClockedObject import ClockedObject
from m5.params import *
@@ -63,8 +63,9 @@
type = 'ArmMMU'
cxx_class = 'gem5::ArmISA::MMU'
cxx_header = 'arch/arm/mmu.hh'
- itb = ArmITB()
- dtb = ArmDTB()
+
+ itb = ArmTLB(entry_type="instruction")
+ dtb = ArmTLB(entry_type="data")
cxx_exports = [
PyBindMethod('wireComponents'),
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index 5c4cca0..e2d61e4 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -51,9 +51,3 @@
class ArmStage2TLB(ArmTLB):
size = 32
is_stage2 = True
-
-class ArmITB(ArmTLB):
- entry_type = "instruction"
-
-class ArmDTB(ArmTLB):
- entry_type = "data"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifc5cf7c41484d4f45b14d1766833ad4c4f7e9e86
Gerrit-Change-Number: 48143
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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