Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48145 )
Change subject: arch: Add a nextLevel pointer to BaseTLB
......................................................................
arch: Add a nextLevel pointer to BaseTLB
This is a step towards supporting multi-level TLBs:
Every TLB will have a pointer to the next level TLB in the
hierarchy.
We are not adding a next_level Param to the BaseTLB as it will
conflict with the SimObject hierarchy. Say we have
* L1 I-TLB
* L1 D-TLB
* L2 shared TLB (I+D)
l2 = BaseTLB()
itb = BaseTLB(next_level=l2)
dtb = BaseTLB(next_level=l2)
The L2 TLB would have two parents and this produces a warning
in gem5.
We are working around this by assigning the nextLevel pointer via
exported C++ methods
JIRA: https://gem5.atlassian.net/browse/GEM5-790
Change-Id: I398a17919564aad4b18efb8dace096965781ece1
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/generic/BaseTLB.py
M src/arch/generic/tlb.hh
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py
index 4fe2338..3deaf57 100644
--- a/src/arch/generic/BaseTLB.py
+++ b/src/arch/generic/BaseTLB.py
@@ -26,7 +26,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.params import *
-from m5.SimObject import SimObject
+from m5.SimObject import PyBindMethod, SimObject
class TypeTLB(ScopedEnum):
"""
@@ -46,6 +46,10 @@
cxx_header = "arch/generic/tlb.hh"
cxx_class = 'gem5::BaseTLB'
+ cxx_exports = [
+ PyBindMethod('setNextLevel'),
+ ]
+
# Ports to connect with other TLB levels
cpu_side_ports = VectorResponsePort("Ports closer to the CPU side")
slave = DeprecatedParam(cpu_side_ports,
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index 7e2ef44..40302dd 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -57,11 +57,13 @@
{
protected:
BaseTLB(const BaseTLBParams &p)
- : SimObject(p), _type(p.entry_type)
+ : SimObject(p), _type(p.entry_type), _nextLevel(nullptr)
{}
TypeTLB _type;
+ BaseTLB *_nextLevel;
+
public:
virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
@@ -119,6 +121,9 @@
void memInvalidate() { flushAll(); }
TypeTLB type() const { return _type; }
+
+ BaseTLB* getNextLevel() const { return _nextLevel; }
+ void setNextLevel(BaseTLB* next_level) { _nextLevel = next_level; }
};
} // namespace gem5
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I398a17919564aad4b18efb8dace096965781ece1
Gerrit-Change-Number: 48145
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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