Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48505 )
Change subject: misc: Replace GEM5_FALLTHROUGH with [[fallthrough]].
......................................................................
misc: Replace GEM5_FALLTHROUGH with [[fallthrough]].
Now that the [[fallthrough]] attribute is standard (as of c++-17), we
can use it directly instead of hiding it behind a macro.
Change-Id: I4d11e35b619532b1a3fd8d042265e18c80d86f9b
---
M src/arch/arm/insts/pred_inst.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/data.isa
M src/arch/arm/isa/formats/fp.isa
M src/arch/arm/isa/formats/sve_top_level.isa
M src/arch/arm/regs/misc.cc
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
M src/arch/arm/utility.cc
M src/arch/sparc/tlb.cc
M src/arch/x86/isa.cc
M src/arch/x86/isa/microops/regop.isa
M src/base/cprintf.cc
M src/base/imgwriter.cc
M src/cpu/kvm/base.cc
M src/cpu/kvm/x86_cpu.cc
M src/dev/arm/smmu_v3.cc
M src/dev/storage/ide_disk.cc
M src/kern/linux/printk.cc
M src/mem/slicc/symbols/Type.py
M src/systemc/dt/fx/scfx_rep.cc
21 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/src/arch/arm/insts/pred_inst.hh
b/src/arch/arm/insts/pred_inst.hh
index f62a2e5..2e35622 100644
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -154,7 +154,7 @@
break;
}
}
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
default:
immValid = false;
break;
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats/aarch64.isa
index ad5238a..afe0b9d 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -595,7 +595,7 @@
return new Unknown64(machInst);
}
}
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
default:
return new Unknown64(machInst);
}
diff --git a/src/arch/arm/isa/formats/data.isa
b/src/arch/arm/isa/formats/data.isa
index b107ed9..33d8d0f 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -1440,7 +1440,7 @@
const uint32_t satImm = bits(machInst, 4, 0);
return new Ssat16(machInst, rd, satImm + 1, rn);
}
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case 0x10:
{
const uint32_t satImm = bits(machInst, 4, 0);
@@ -1473,7 +1473,7 @@
const uint32_t satImm = bits(machInst, 4, 0);
return new Usat16(machInst, rd, satImm, rn);
}
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case 0x18:
{
const uint32_t satImm = bits(machInst, 4, 0);
diff --git a/src/arch/arm/isa/formats/fp.isa
b/src/arch/arm/isa/formats/fp.isa
index 2ed5c26..b21ef53 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -131,7 +131,7 @@
width = 1;
break;
}
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
default:
return new Unknown(machInst);
}
@@ -2113,7 +2113,7 @@
false, true, true, offset);
}
}
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case 0x3:
const bool up = (bits(machInst, 23) == 1);
const uint32_t imm = bits(machInst, 7, 0) << 2;
diff --git a/src/arch/arm/isa/formats/sve_top_level.isa
b/src/arch/arm/isa/formats/sve_top_level.isa
index 43cdea5..803029a 100644
--- a/src/arch/arm/isa/formats/sve_top_level.isa
+++ b/src/arch/arm/isa/formats/sve_top_level.isa
@@ -248,7 +248,7 @@
case 4:
if (!bits(machInst, 10))
return decodeSveFpMulIndexed(machInst);
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
default:
return new Unknown64(machInst);
}
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 0306e9f..3d679bb 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2868,7 +2868,7 @@
}
break;
}
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
default:
// S3_<op1>_11_<Cm>_<op2>
return MISCREG_IMPDEF_UNIMPL;
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 5632be1..8edf891 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -1654,7 +1654,7 @@
case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient
case 0x9 ... 0xb: // Normal Memory, Inner Write-through
non-transient
warn_if(!attr_hi, "Unpredictable behavior");
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case 0x4: // Device-nGnRE memory or
// Normal memory, Inner Non-cacheable
case 0x8: // Device-nGRE memory or
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 8941f9e..703416b 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -943,7 +943,7 @@
grant_read = false;
break;
}
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case EL3:
{
uint8_t perm = (ap & 0x2) | xn;
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 68a1115..4c1acb5 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -144,7 +144,7 @@
// be part of the table even if MPIDR is not accessible in user
// mode.
warn_once("Trying to read MPIDR at EL0\n");
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case EL1:
if (ArmSystem::haveEL(tc, EL2) && !is_secure)
return tc->readMiscReg(MISCREG_VMPIDR_EL2);
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index f260e71..0e034c8 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -1252,7 +1252,7 @@
break;
case ASI_ITLB_DATA_ACCESS_REG:
entry_insert = bits(va, 8,3);
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case ASI_ITLB_DATA_IN_REG:
assert(entry_insert != -1 || mbits(va,10,9) == va);
ta_insert = itb->tag_access;
@@ -1267,7 +1267,7 @@
break;
case ASI_DTLB_DATA_ACCESS_REG:
entry_insert = bits(va, 8,3);
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case ASI_DTLB_DATA_IN_REG:
assert(entry_insert != -1 || mbits(va,10,9) == va);
ta_insert = tag_access;
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 085420e..8f1d401 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -381,7 +381,7 @@
break;
case MISCREG_DR4:
miscReg = MISCREG_DR6;
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case MISCREG_DR6:
{
DR6 dr6 = regVal[MISCREG_DR6];
@@ -398,7 +398,7 @@
break;
case MISCREG_DR5:
miscReg = MISCREG_DR7;
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case MISCREG_DR7:
{
DR7 dr7 = regVal[MISCREG_DR7];
diff --git a/src/arch/x86/isa/microops/regop.isa
b/src/arch/x86/isa/microops/regop.isa
index 10bf8f7..d12af41 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -1504,7 +1504,7 @@
fault = std::make_shared<GeneralProtection>(selector);
break;
}
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case SegIntGateCheck:
// Make sure the gate's the right type.
if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) ||
diff --git a/src/base/cprintf.cc b/src/base/cprintf.cc
index 327b735..28855fb 100644
--- a/src/base/cprintf.cc
+++ b/src/base/cprintf.cc
@@ -142,7 +142,7 @@
case 'X':
fmt.uppercase = true;
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case 'x':
fmt.base = Format::Hex;
fmt.format = Format::Integer;
@@ -164,7 +164,7 @@
case 'G':
fmt.uppercase = true;
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case 'g':
fmt.format = Format::Floating;
fmt.floatFormat = Format::Best;
@@ -173,7 +173,7 @@
case 'E':
fmt.uppercase = true;
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case 'e':
fmt.format = Format::Floating;
fmt.floatFormat = Format::Scientific;
@@ -220,7 +220,7 @@
fmt.fillZero = true;
break;
}
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case '1':
case '2':
case '3':
diff --git a/src/base/imgwriter.cc b/src/base/imgwriter.cc
index c9bc289..fb402ba 100644
--- a/src/base/imgwriter.cc
+++ b/src/base/imgwriter.cc
@@ -60,7 +60,7 @@
// gem5 will try PNG first, and it will fallback to BMP if not
// available.
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
#if HAVE_PNG
case enums::Png:
return std::unique_ptr<PngWriter>(new PngWriter(fb));
diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index b43bee5..c7c72a8 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -337,7 +337,7 @@
deschedule(tickEvent);
_status = Idle;
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case Idle:
// Idle, no need to drain
assert(!tickEvent.scheduled());
diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc
index 7097470..899bbce 100644
--- a/src/cpu/kvm/x86_cpu.cc
+++ b/src/cpu/kvm/x86_cpu.cc
@@ -403,7 +403,7 @@
case MISCREG_ES:
if (seg.unusable)
break;
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case MISCREG_CS:
if (seg.base & 0xffffffff00000000ULL)
warn("Illegal %s base: 0x%x\n", name, seg.base);
@@ -441,7 +441,7 @@
case 3:
if (sregs.cs.type == 3 && seg.dpl != 0)
warn("CS type is 3, but SS DPL is != 0.\n");
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case 7:
if (!(sregs.cr0 & 1) && seg.dpl != 0)
warn("SS DPL is %i, but CR0 PE is 0\n", seg.dpl);
@@ -485,7 +485,7 @@
case MISCREG_GS:
if (seg.unusable)
break;
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case MISCREG_CS:
if (!seg.s)
warn("%s: S flag not set\n", name);
@@ -494,7 +494,7 @@
case MISCREG_TSL:
if (seg.unusable)
break;
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case MISCREG_TR:
if (seg.s)
warn("%s: S flag is set\n", name);
@@ -510,7 +510,7 @@
case MISCREG_TSL:
if (seg.unusable)
break;
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case MISCREG_TR:
case MISCREG_CS:
if (!seg.present)
diff --git a/src/dev/arm/smmu_v3.cc b/src/dev/arm/smmu_v3.cc
index ac71023..03fe2ef 100644
--- a/src/dev/arm/smmu_v3.cc
+++ b/src/dev/arm/smmu_v3.cc
@@ -253,7 +253,7 @@
pkt = action.pkt;
break;
}
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case ACTION_SEND_REQ_FINAL:
delay += requestPort.sendAtomic(action.pkt);
pkt = action.pkt;
@@ -309,7 +309,7 @@
break;
}
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case ACTION_SEND_REQ_FINAL:
action.pkt->pushSenderState(proc);
diff --git a/src/dev/storage/ide_disk.cc b/src/dev/storage/ide_disk.cc
index 4c4e75b..a7185e4 100644
--- a/src/dev/storage/ide_disk.cc
+++ b/src/dev/storage/ide_disk.cc
@@ -687,7 +687,7 @@
// Supported DMA commands
case WDCC_WRITEDMA:
dmaRead = true; // a write to the disk is a DMA read from memory
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case WDCC_READDMA:
if (!(cmdReg.drive & DRIVE_LBA_BIT))
panic("Attempt to perform CHS access, only supports LBA\n");
diff --git a/src/kern/linux/printk.cc b/src/kern/linux/printk.cc
index 9a5b963..c356016 100644
--- a/src/kern/linux/printk.cc
+++ b/src/kern/linux/printk.cc
@@ -111,7 +111,7 @@
break;
case 'P':
format = true;
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case 'p':
hexnum = true;
break;
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index 628a0ac..93eeaf7 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -775,7 +775,7 @@
code(' base +=
${{enum.ident}}_Controller::getNumControllers();')
else:
code(' base += 0;')
- code(' GEM5_FALLTHROUGH;')
+ code(' [[fallthrough]];')
code(' case ${{self.c_ident}}_${{enum.ident}}:')
code(' break;')
code.dedent()
diff --git a/src/systemc/dt/fx/scfx_rep.cc b/src/systemc/dt/fx/scfx_rep.cc
index 183ccdb..7bb2318 100644
--- a/src/systemc/dt/fx/scfx_rep.cc
+++ b/src/systemc/dt/fx/scfx_rep.cc
@@ -549,10 +549,10 @@
switch (*s) {
case '1':
set_bin(j);
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case '0':
j--;
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case '.':
break;
default:
@@ -587,10 +587,10 @@
case '7': case '6': case '5': case '4':
case '3': case '2': case '1':
set_oct(j, *s - '0');
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case '0':
j -= 3;
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case '.':
break;
default:
@@ -677,10 +677,10 @@
case '9': case '8': case '7': case '6': case '5':
case '4': case '3': case '2': case '1':
set_hex(j, *s - '0');
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case '0':
j -= 4;
- GEM5_FALLTHROUGH;
+ [[fallthrough]];
case '.':
break;
default:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4d11e35b619532b1a3fd8d042265e18c80d86f9b
Gerrit-Change-Number: 48505
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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