Quentin Forcioli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48544 )
Change subject: arch-arm,dev-arm: Running OPTEE to boot on gem5
......................................................................
arch-arm,dev-arm: Running OPTEE to boot on gem5
The OPTEE I boot is built using ARM "Running Trusted Firmware-A on gem5"
tutorial from ARM
(https://community.arm.com/developer/research/b/articles/posts/running-trusted-firmware-a-on-gem5)
and OPTEE repositories
(https://optee.readthedocs.io/en/latest/building/gits/index.html).
-Changed IRQ/FIQ behavior: taking into account that FIQ and IRQ can
transform into each other when they belong to group 1.
-Change El2S behavior: prevent a disabled EL2S to trap anything from EL1S
-ARM Foundation platform: add devices that are need to boot OPTEE
(respecting ARM specifications)
Change-Id: Ifd3ed698f766e5aef7f4af0bfb43094be188f446
---
M src/arch/arm/insts/misc64.cc
M src/arch/arm/interrupts.cc
M src/arch/arm/interrupts.hh
M src/arch/arm/isa.hh
M src/dev/arm/RealView.py
M src/dev/arm/gic_v3_cpu_interface.hh
6 files changed, 47 insertions(+), 8 deletions(-)
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 0f301b0..88810ab 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -191,6 +191,9 @@
const HDCR mdcr = tc->readMiscReg(MISCREG_MDCR_EL3);
bool trap_to_hyp = false;
+ //don't trap to EL2 from EL1s if EL2S is not enabled
+ if (isSecure(tc)!= IsSecureEL2Enabled(tc))
+ return false;
switch (misc_reg) {
case MISCREG_IMPDEF_UNIMPL:
diff --git a/src/arch/arm/interrupts.cc b/src/arch/arm/interrupts.cc
index b0f18df..7010e6b 100644
--- a/src/arch/arm/interrupts.cc
+++ b/src/arch/arm/interrupts.cc
@@ -36,8 +36,9 @@
*/
#include "arch/arm/interrupts.hh"
-
+#include "arch/arm/isa.hh"
#include "arch/arm/system.hh"
+#include "dev/arm/gic_v3_cpu_interface.hh"
namespace gem5
{
@@ -159,4 +160,16 @@
(mask != INT_MASK_P);
}
+void ArmISA::Interrupts::checkForFiqIrqMutation() const
+{
+ //TODO check if pending IRQ is from G1S or G1NS
+ ISA* isa=static_cast<ISA*>(tc->getIsaPtr());
+ if (isa->haveGICv3CpuIfc()) {
+ Gicv3CPUInterface& interf=dynamic_cast<Gicv3CPUInterface&>(
+ isa->getGICv3CPUInterface()
+ );
+ interf.update();
+ }
+}
+
} // namespace gem5
diff --git a/src/arch/arm/interrupts.hh b/src/arch/arm/interrupts.hh
index 2f99d6e..2bd3dc6 100644
--- a/src/arch/arm/interrupts.hh
+++ b/src/arch/arm/interrupts.hh
@@ -128,6 +128,10 @@
};
bool takeInt(InterruptTypes int_type) const;
+ //this function check for FIQ or IRQ that changed nature of interrupt
+ //because of EL change
+ //(G1NS et G1S IRQ are FIQ if not in the right security setting)
+ void checkForFiqIrqMutation() const;
bool
checkInterrupts() const override
@@ -164,9 +168,15 @@
bool take_irq = takeInt(INT_IRQ);
bool take_fiq = takeInt(INT_FIQ);
bool take_ea = takeInt(INT_ABT);
-
- return ((interrupts[INT_IRQ] && take_irq) ||
- (interrupts[INT_FIQ] && take_fiq) ||
+ bool is_irq =(interrupts[INT_IRQ] && take_irq);
+ bool is_fiq =(interrupts[INT_FIQ] && take_fiq);
+ if (is_irq || is_fiq) {
+ checkForFiqIrqMutation();
+ is_irq =(interrupts[INT_IRQ] && take_irq);
+ is_fiq =(interrupts[INT_FIQ] && take_fiq);
+ }
+ return ( is_irq ||
+ is_fiq ||
(interrupts[INT_ABT] && take_ea) ||
((interrupts[INT_VIRT_IRQ] || hcr.vi) && allowVIrq) ||
((interrupts[INT_VIRT_FIQ] || hcr.vf) && allowVFiq) ||
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index cc6e54d..5c4ccf2 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -499,7 +499,6 @@
}
BaseISADevice &getGenericTimer();
- BaseISADevice &getGICv3CPUInterface();
private:
void assert32() { assert(((CPSR)readMiscReg(MISCREG_CPSR)).width);
}
@@ -889,6 +888,8 @@
return gicv3CpuInterface != nullptr;
}
+ BaseISADevice &getGICv3CPUInterface();
+
enums::VecRegRenameMode
initVecRegRenameMode() const override
{
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 919ff63..91fd4da 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1430,10 +1430,19 @@
pci_pio_base=0x50000000,
pci_mem_base=0x4000000000,
int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
+ #flash1 have to be a SimpleMemory to keep
+ #support for u-boot vexpress_aemv8a configuration
+ flash1 = SimpleMemory(range=AddrRange(0x0c000000, 0x10000000),
+ conf_table_reported=False)
+ #TODO: preventing access from unsecure world to the trusted RAM
+ trusted_dram=SimpleMemory(range=AddrRange(0x6000000, size='32MB'),
+ conf_table_reported=False)
+ fake_scu= AmbaFake(pio_addr=0x2c000000, ignore_access=True)
def _on_chip_devices(self):
return super(VExpress_GEM5_Foundation, self)._on_chip_devices() + [
- self.gic
+ self.gic,
+ self.fake_scu
]
def _off_chip_devices(self):
@@ -1441,7 +1450,10 @@
self.clcd,
self.sp810_fake,
]
-
+ def _on_chip_memory(self):
+ return super(VExpress_GEM5_Foundation, self)._on_chip_memory() + [
+ self.trusted_dram
+ ]
def setupBootLoader(self, cur_sys, loc, boot_loader=None):
if boot_loader is None:
boot_loader = [ loc('boot_v2.arm64') ]
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh
b/src/dev/arm/gic_v3_cpu_interface.hh
index 9f60d84..fa2ca55 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -53,7 +53,7 @@
class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
{
private:
-
+ friend class ArmISA::Interrupts;
friend class Gicv3Distributor;
friend class Gicv3Redistributor;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48544
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifd3ed698f766e5aef7f4af0bfb43094be188f446
Gerrit-Change-Number: 48544
Gerrit-PatchSet: 1
Gerrit-Owner: Quentin Forcioli <quentin.forci...@telecom-paris.fr>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
