Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48607 )
Change subject: mem,sim: Replace the deprecated chatty_assert with
gem5_assert.
......................................................................
mem,sim: Replace the deprecated chatty_assert with gem5_assert.
The new gem5_assert macro now does the job of both regular asserts, and
chatty_assert, except that its condition must always be valid code. It
is still not evaluated if NDEBUG is set, though.
Change-Id: I7c9435311746b2e02fe7335bce6ba618bf9fd4eb
---
M src/mem/cache/base.cc
M src/mem/cache/cache.cc
M src/mem/mem_checker.cc
M src/sim/voltage_domain.cc
M src/sim/voltage_domain.hh
5 files changed, 24 insertions(+), 23 deletions(-)
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 5f7d81b..4e532e0 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1156,9 +1156,9 @@
// sanity check
assert(pkt->isRequest());
- chatty_assert(!(isReadOnly && pkt->isWrite()),
- "Should never see a write in a read-only cache %s\n",
- name());
+ gem5_assert(!(isReadOnly && pkt->isWrite()),
+ "Should never see a write in a read-only cache %s\n",
+ name());
// Access block in the tags
Cycles tag_latency(0);
@@ -1501,8 +1501,8 @@
// owners copy
blk->setCoherenceBits(CacheBlk::DirtyBit);
- chatty_assert(!isReadOnly, "Should never see dirty snoop
response "
- "in read-only cache %s\n", name());
+ gem5_assert(!isReadOnly, "Should never see dirty snoop
response "
+ "in read-only cache %s\n", name());
}
}
@@ -1615,8 +1615,8 @@
PacketPtr
BaseCache::writebackBlk(CacheBlk *blk)
{
- chatty_assert(!isReadOnly || writebackClean,
- "Writeback from read-only cache");
+ gem5_assert(!isReadOnly || writebackClean,
+ "Writeback from read-only cache");
assert(blk && blk->isValid() &&
(blk->isSet(CacheBlk::DirtyBit) || writebackClean));
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 7ea8a8c..29e52db 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -165,9 +165,9 @@
if (pkt->req->isUncacheable()) {
assert(pkt->isRequest());
- chatty_assert(!(isReadOnly && pkt->isWrite()),
- "Should never see a write in a read-only cache %s\n",
- name());
+ gem5_assert(!(isReadOnly && pkt->isWrite()),
+ "Should never see a write in a read-only cache %s\n",
+ name());
DPRINTF(Cache, "%s for %s\n", __func__, pkt->print());
@@ -1104,7 +1104,7 @@
// xbar.
respond = blk->isSet(CacheBlk::DirtyBit) && pkt->needsResponse();
- chatty_assert(!(isReadOnly && blk->isSet(CacheBlk::DirtyBit)),
+ gem5_assert(!(isReadOnly && blk->isSet(CacheBlk::DirtyBit)),
"Should never have a dirty block in a read-only cache %s\n",
name());
}
diff --git a/src/mem/mem_checker.cc b/src/mem/mem_checker.cc
index d8a3ee9..b331c84 100644
--- a/src/mem/mem_checker.cc
+++ b/src/mem/mem_checker.cc
@@ -53,7 +53,7 @@
// Initialize a fresh write cluster
start = _start;
}
- chatty_assert(start <= _start, "WriteClusters must filled in order!");
+ gem5_assert(start <= _start, "WriteClusters must filled in order!");
++numIncomplete;
diff --git a/src/sim/voltage_domain.cc b/src/sim/voltage_domain.cc
index b8debaa..297c23f 100644
--- a/src/sim/voltage_domain.cc
+++ b/src/sim/voltage_domain.cc
@@ -64,9 +64,9 @@
void
VoltageDomain::perfLevel(PerfLevel perf_level)
{
- chatty_assert(perf_level < voltageOpPoints.size(),
- "DVFS: Requested voltage ID %d is outside the known "\
- "range for domain %s.\n", perf_level, name());
+ gem5_assert(perf_level < voltageOpPoints.size(),
+ "DVFS: Requested voltage ID %d is outside the known "\
+ "range for domain %s.\n", perf_level, name());
if (perf_level == _perfLevel) {
// Silently ignore identical overwrites
@@ -88,11 +88,12 @@
// Find the highest requested performance level and update the voltage
// domain with it
PerfLevel perf_max = (PerfLevel)-1;
- for (auto dit = srcClockChildren.begin(); dit !=
srcClockChildren.end(); ++dit) {
+ for (auto dit = srcClockChildren.begin(); dit !=
srcClockChildren.end();
+ ++dit) {
SrcClockDomain* d = *dit;
- chatty_assert(d->voltageDomain() == this, "DVFS: Clock domain %s "\
- "(id: %d) should not be registered with voltage
domain "\
- "%s\n", d->name(), d->domainID(), name());
+ gem5_assert(d->voltageDomain() == this, "DVFS: Clock domain %s "\
+ "(id: %d) should not be registered with voltage
domain "\
+ "%s\n", d->name(), d->domainID(), name());
PerfLevel perf = d->perfLevel();
diff --git a/src/sim/voltage_domain.hh b/src/sim/voltage_domain.hh
index 5fbfa53..3822f89 100644
--- a/src/sim/voltage_domain.hh
+++ b/src/sim/voltage_domain.hh
@@ -77,10 +77,10 @@
*/
double voltage(PerfLevel perf_level) const
{
- chatty_assert(perf_level < numVoltages(), "VoltageDomain %s "\
- "request for voltage perf level %u is outside "\
- "of numVoltages %u", name(), perf_level,
- numVoltages());
+ gem5_assert(perf_level < numVoltages(), "VoltageDomain %s "\
+ "request for voltage perf level %u is outside "\
+ "of numVoltages %u", name(), perf_level,
+ numVoltages());
return voltageOpPoints[perf_level];
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7c9435311746b2e02fe7335bce6ba618bf9fd4eb
Gerrit-Change-Number: 48607
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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