[gem5-dev] Change in gem5/gem5[develop]: cpu: Add generalized register accessors setReg and getReg.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49107 )

Change subject: cpu: Add generalized register accessors setReg and getReg.
......................................................................

cpu: Add generalized register accessors setReg and getReg.

These will read registers of any type, as described by a RegId. These
currently have default implementations which just delegate to the
existing, register type specific accessors.

Change-Id: I980ca15b3acd9a5a796c977276201d64c69398b8
---
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
2 files changed, 112 insertions(+), 0 deletions(-)



diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 4852111..6b3c4f9 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -153,6 +153,106 @@
     getSystemPtr()->threads.quiesceTick(contextId(), resume);
 }

+RegVal
+ThreadContext::getReg(const RegId &reg) const
+{
+    return getRegFlat(flattenRegId(reg));
+}
+
+void
+ThreadContext::setReg(const RegId &reg, RegVal val)
+{
+    setRegFlat(flattenRegId(reg), val);
+}
+
+void
+ThreadContext::getReg(const RegId &reg, void *val) const
+{
+    getRegFlat(flattenRegId(reg), val);
+}
+
+void
+ThreadContext::setReg(const RegId &reg, const void *val)
+{
+    setRegFlat(flattenRegId(reg), val);
+}
+
+RegVal
+ThreadContext::getRegFlat(const RegId &reg) const
+{
+    RegVal val;
+    getRegFlat(reg, &val);
+    return val;
+}
+
+void
+ThreadContext::setRegFlat(const RegId &reg, RegVal val)
+{
+    setRegFlat(reg, &val);
+}
+
+void
+ThreadContext::getRegFlat(const RegId &reg, void *val) const
+{
+    const RegIndex idx = reg.index();
+    const RegClassType type = reg.classValue();
+    switch (type) {
+      case IntRegClass:
+        *(RegVal *)val = readIntRegFlat(idx);
+        break;
+      case FloatRegClass:
+        *(RegVal *)val = readFloatRegFlat(idx);
+        break;
+      case VecRegClass:
+        *(TheISA::VecRegContainer *)val = readVecRegFlat(idx);
+        break;
+      case VecPredRegClass:
+        *(TheISA::VecPredRegContainer *)val = readVecPredRegFlat(idx);
+        break;
+      case CCRegClass:
+        *(RegVal *)val = readCCRegFlat(idx);
+        break;
+      case MiscRegClass:
+        panic("MiscRegs should not be read with getReg.");
+      case VecElemClass:
+        *(TheISA::VecElem *)val = readVecElemFlat(idx, reg.elemIndex());
+        break;
+      default:
+        panic("Unrecognized register class type %d.", type);
+    }
+}
+
+void
+ThreadContext::setRegFlat(const RegId &reg, const void *val)
+{
+    const RegIndex idx = reg.index();
+    const RegClassType type = reg.classValue();
+    switch (type) {
+      case IntRegClass:
+        setIntRegFlat(idx, *(RegVal *)val);
+        break;
+      case FloatRegClass:
+        setFloatRegFlat(idx, *(RegVal *)val);
+        break;
+      case VecRegClass:
+        setVecRegFlat(idx, *(TheISA::VecRegContainer *)val);
+        break;
+      case VecPredRegClass:
+        setVecPredRegFlat(idx, *(TheISA::VecPredRegContainer *)val);
+        break;
+      case CCRegClass:
+        setCCRegFlat(idx, *(RegVal *)val);
+        break;
+      case MiscRegClass:
+        panic("MiscRegs should not be read with getReg.");
+      case VecElemClass:
+        setVecElemFlat(idx, reg.elemIndex(), *(TheISA::VecElem *)val);
+        break;
+      default:
+        panic("Unrecognized register class type %d.", type);
+    }
+}
+
 void
 serialize(const ThreadContext &tc, CheckpointOut &cp)
 {
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index bbe084a..e0ecd16 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -192,6 +192,12 @@
     //
     // New accessors for new decoder.
     //
+    virtual RegVal getReg(const RegId &reg) const;
+    virtual void getReg(const RegId &reg, void *val) const;
+
+    virtual void setReg(const RegId &reg, RegVal val);
+    virtual void setReg(const RegId &reg, const void *val);
+
     virtual RegVal readIntReg(RegIndex reg_idx) const = 0;

     virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
@@ -279,6 +285,12 @@
      * serialization code to access all registers.
      */

+    virtual RegVal getRegFlat(const RegId &reg) const;
+    virtual void getRegFlat(const RegId &reg, void *val) const;
+
+    virtual void setRegFlat(const RegId &reg, RegVal val);
+    virtual void setRegFlat(const RegId &reg, const void *val);
+
     virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
     virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I980ca15b3acd9a5a796c977276201d64c69398b8
Gerrit-Change-Number: 49107
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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