Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49108 )
Change subject: cpu: Fix style in src/cpu/o3/cpu.hh.
......................................................................
cpu: Fix style in src/cpu/o3/cpu.hh.
Change-Id: I08802e184dfc0c9b4d96bc3ddf07af3a3a7f4e81
---
M src/cpu/o3/cpu.hh
1 file changed, 34 insertions(+), 19 deletions(-)
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index f5197b2..412bb18 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -123,7 +123,8 @@
EventFunctionWrapper threadExitEvent;
/** Schedule tick event, regardless of its current state. */
- void scheduleTickEvent(Cycles delay)
+ void
+ scheduleTickEvent(Cycles delay)
{
if (tickEvent.squashed())
reschedule(tickEvent, clockEdge(delay));
@@ -132,7 +133,8 @@
}
/** Unschedule tick event, regardless of its current state. */
- void unscheduleTickEvent()
+ void
+ unscheduleTickEvent()
{
if (tickEvent.scheduled())
tickEvent.squash();
@@ -192,8 +194,11 @@
void startup() override;
/** Returns the Number of Active Threads in the CPU */
- int numActiveThreads()
- { return activeThreads.size(); }
+ int
+ numActiveThreads()
+ {
+ return activeThreads.size();
+ }
/** Add Thread to Active Threads List */
void activateThread(ThreadID tid);
@@ -274,8 +279,7 @@
void verifyMemoryMode() const override;
/** Get the current instruction sequence number, and increment it. */
- InstSeqNum getAndIncrementInstSeq()
- { return globalSeqNum++; }
+ InstSeqNum getAndIncrementInstSeq() { return globalSeqNum++; }
/** Traps to handle given fault. */
void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
@@ -336,8 +340,11 @@
enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
/** Sets the current vector renaming mode */
- void vecRenameMode(enums::VecRegRenameMode vec_mode)
- { vecMode = vec_mode; }
+ void
+ vecRenameMode(enums::VecRegRenameMode vec_mode)
+ {
+ vecMode = vec_mode;
+ }
const TheISA::VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
@@ -568,12 +575,18 @@
void activityThisCycle() { activityRec.activity(); }
/** Changes a stage's status to active within the activity recorder. */
- void activateStage(const StageIdx idx)
- { activityRec.activateStage(idx); }
+ void
+ activateStage(const StageIdx idx)
+ {
+ activityRec.activateStage(idx);
+ }
/** Changes a stage's status to inactive within the activity recorder.
*/
- void deactivateStage(const StageIdx idx)
- { activityRec.deactivateStage(idx); }
+ void
+ deactivateStage(const StageIdx idx)
+ {
+ activityRec.deactivateStage(idx);
+ }
/** Wakes the CPU, rescheduling the CPU if it's not already active. */
void wakeCPU();
@@ -622,11 +635,11 @@
std::vector<ThreadID> tids;
/** CPU pushRequest function, forwards request to LSQ. */
- Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
- unsigned int size, Addr addr, Request::Flags flags,
- uint64_t *res, AtomicOpFunctorPtr amo_op = nullptr,
- const std::vector<bool>& byte_enable =
- std::vector<bool>())
+ Fault
+ pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
+ unsigned int size, Addr addr, Request::Flags flags,
+ uint64_t *res, AtomicOpFunctorPtr amo_op = nullptr,
+ const std::vector<bool>& byte_enable=std::vector<bool>())
{
return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr,
@@ -634,13 +647,15 @@
}
/** CPU read function, forwards read to LSQ. */
- Fault read(LSQRequest* req, int load_idx)
+ Fault
+ read(LSQRequest* req, int load_idx)
{
return iew.ldstQueue.read(req, load_idx);
}
/** CPU write function, forwards write to LSQ. */
- Fault write(LSQRequest* req, uint8_t *data, int store_idx)
+ Fault
+ write(LSQRequest* req, uint8_t *data, int store_idx)
{
return iew.ldstQueue.write(req, data, store_idx);
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I08802e184dfc0c9b4d96bc3ddf07af3a3a7f4e81
Gerrit-Change-Number: 49108
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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