Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49109 )
Change subject: cpu: Implement getReg and setReg for O3.
......................................................................
cpu: Implement getReg and setReg for O3.
Change-Id: I3f0bf1e75a5191be98c79fede5aad854a920e9c9
---
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/regfile.hh
M src/cpu/o3/thread_context.cc
M src/cpu/o3/thread_context.hh
5 files changed, 326 insertions(+), 0 deletions(-)
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 1743857..fdb7123 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1143,6 +1143,30 @@
}
RegVal
+CPU::getReg(PhysRegIdPtr phys_reg)
+{
+ return regFile.getReg(phys_reg);
+}
+
+void
+CPU::getReg(PhysRegIdPtr phys_reg, void *val)
+{
+ regFile.getReg(phys_reg, val);
+}
+
+void
+CPU::setReg(PhysRegIdPtr phys_reg, RegVal val)
+{
+ regFile.setReg(phys_reg, val);
+}
+
+void
+CPU::setReg(PhysRegIdPtr phys_reg, const void *val)
+{
+ regFile.setReg(phys_reg, val);
+}
+
+RegVal
CPU::readIntReg(PhysRegIdPtr phys_reg)
{
cpuStats.intRegfileReads++;
@@ -1242,6 +1266,114 @@
}
RegVal
+CPU::getArchReg(const RegId ®, ThreadID tid)
+{
+ switch (reg.classValue()) {
+ case IntRegClass:
+ cpuStats.intRegfileReads++;
+ break;
+ case FloatRegClass:
+ cpuStats.fpRegfileReads++;
+ break;
+ case CCRegClass:
+ cpuStats.ccRegfileReads++;
+ break;
+ case VecRegClass:
+ case VecElemClass:
+ cpuStats.vecRegfileReads++;
+ break;
+ case VecPredRegClass:
+ cpuStats.vecPredRegfileReads++;
+ break;
+ default:
+ break;
+ }
+ PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(reg);
+ return getReg(phys_reg);
+}
+
+void
+CPU::getArchReg(const RegId ®, void *val, ThreadID tid)
+{
+ switch (reg.classValue()) {
+ case IntRegClass:
+ cpuStats.intRegfileReads++;
+ break;
+ case FloatRegClass:
+ cpuStats.fpRegfileReads++;
+ break;
+ case CCRegClass:
+ cpuStats.ccRegfileReads++;
+ break;
+ case VecRegClass:
+ case VecElemClass:
+ cpuStats.vecRegfileReads++;
+ break;
+ case VecPredRegClass:
+ cpuStats.vecPredRegfileReads++;
+ break;
+ default:
+ break;
+ }
+ PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(reg);
+ getReg(phys_reg, val);
+}
+
+void
+CPU::setArchReg(const RegId ®, RegVal val, ThreadID tid)
+{
+ switch (reg.classValue()) {
+ case IntRegClass:
+ cpuStats.intRegfileWrites++;
+ break;
+ case FloatRegClass:
+ cpuStats.fpRegfileWrites++;
+ break;
+ case CCRegClass:
+ cpuStats.ccRegfileWrites++;
+ break;
+ case VecRegClass:
+ case VecElemClass:
+ cpuStats.vecRegfileWrites++;
+ break;
+ case VecPredRegClass:
+ cpuStats.vecPredRegfileWrites++;
+ break;
+ default:
+ break;
+ }
+ PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(reg);
+ setReg(phys_reg, val);
+}
+
+void
+CPU::setArchReg(const RegId ®, const void *val, ThreadID tid)
+{
+ switch (reg.classValue()) {
+ case IntRegClass:
+ cpuStats.intRegfileWrites++;
+ break;
+ case FloatRegClass:
+ cpuStats.fpRegfileWrites++;
+ break;
+ case CCRegClass:
+ cpuStats.ccRegfileWrites++;
+ break;
+ case VecRegClass:
+ case VecElemClass:
+ cpuStats.vecRegfileWrites++;
+ break;
+ case VecPredRegClass:
+ cpuStats.vecPredRegfileWrites++;
+ break;
+ default:
+ break;
+ }
+ PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(reg);
+ setReg(phys_reg, val);
+}
+
+RegVal
CPU::readArchIntReg(int reg_idx, ThreadID tid)
{
cpuStats.intRegfileReads++;
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 412bb18..75f2565 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -325,6 +325,12 @@
*/
void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
+ RegVal getReg(PhysRegIdPtr phys_reg);
+ void getReg(PhysRegIdPtr phys_reg, void *val);
+
+ void setReg(PhysRegIdPtr phys_reg, RegVal val);
+ void setReg(PhysRegIdPtr phys_reg, const void *val);
+
RegVal readIntReg(PhysRegIdPtr phys_reg);
RegVal readFloatReg(PhysRegIdPtr phys_reg);
@@ -368,6 +374,12 @@
void setCCReg(PhysRegIdPtr phys_reg, RegVal val);
+ RegVal getArchReg(const RegId ®, ThreadID tid);
+ void getArchReg(const RegId ®, void *val, ThreadID tid);
+
+ void setArchReg(const RegId ®, RegVal val, ThreadID tid);
+ void setArchReg(const RegId ®, const void *val, ThreadID tid);
+
RegVal readArchIntReg(int reg_idx, ThreadID tid);
RegVal readArchFloatReg(int reg_idx, ThreadID tid);
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 3c8ebdb..4ed1d24 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -42,6 +42,7 @@
#ifndef __CPU_O3_REGFILE_HH__
#define __CPU_O3_REGFILE_HH__
+#include <cstring>
#include <vector>
#include "arch/generic/isa.hh"
@@ -105,6 +106,18 @@
data.data() + (idx << _regShift));
}
+ void
+ get(size_t idx, void *val) const
+ {
+ std::memcpy(val, data.data() + (idx << _regShift), _regBytes);
+ }
+
+ void
+ set(size_t idx, const void *val)
+ {
+ std::memcpy(data.data() + (idx << _regShift), val, _regBytes);
+ }
+
void clear() { std::fill(data.begin(), data.end(), 0); }
};
@@ -214,6 +227,143 @@
return &miscRegIds[reg_idx];
}
+ RegVal
+ getReg(PhysRegIdPtr phys_reg) const
+ {
+ const RegClassType type = phys_reg->classValue();
+ const RegIndex idx = phys_reg->index();
+
+ RegVal val;
+ switch (type) {
+ case IntRegClass:
+ val = intRegFile.reg(idx);
+ DPRINTF(IEW, "RegFile: Access to int register %i, has data
#x\n",
+ idx, val);
+ return val;
+ case FloatRegClass:
+ val = floatRegFile.reg(idx);
+ DPRINTF(IEW, "RegFile: Access to float register %i has
data %#x\n",
+ idx, val);
+ return val;
+ case CCRegClass:
+ val = ccRegFile.reg(idx);
+ DPRINTF(IEW, "RegFile: Access to cc register %i has
data %#x\n",
+ idx, val);
+ return val;
+ default:
+ panic("Unsupported register class type %d.", type);
+ }
+ }
+
+ void
+ getReg(PhysRegIdPtr phys_reg, void *val) const
+ {
+ const RegClassType type = phys_reg->classValue();
+ const RegIndex idx = phys_reg->index();
+
+ switch (type) {
+ case IntRegClass:
+ *(RegVal *)val = getReg(phys_reg);
+ break;
+ case FloatRegClass:
+ *(RegVal *)val = getReg(phys_reg);
+ break;
+ case VecRegClass:
+ vectorRegFile.get(idx, val);
+ DPRINTF(IEW, "RegFile: Access to vector register %i, has "
+ "data %s\n", idx, *(TheISA::VecRegContainer *)val);
+ break;
+ case VecPredRegClass:
+ vecPredRegFile.get(idx, val);
+ DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
+ "data %s\n", idx, *(TheISA::VecRegContainer *)val);
+ break;
+ case CCRegClass:
+ *(RegVal *)val = getReg(phys_reg);
+ break;
+ case VecElemClass:
+ {
+ auto ret = vectorRegFile.reg<TheISA::VecRegContainer>(
+ idx).as<TheISA::VecElem>();
+ const TheISA::VecElem &elem = ret[phys_reg->elemIndex()];
+ DPRINTF(IEW, "RegFile: Access to element %d of vector "
+ "register %i, has data %#x\n",
phys_reg->elemIndex(),
+ idx, elem);
+ memcpy(val, &elem, sizeof(elem));
+ }
+ break;
+ default:
+ panic("Unrecognized register class type %d.", type);
+ }
+ }
+
+ void
+ setReg(PhysRegIdPtr phys_reg, RegVal val)
+ {
+ const RegClassType type = phys_reg->classValue();
+ const RegIndex idx = phys_reg->index();
+
+ switch (type) {
+ case IntRegClass:
+ intRegFile.reg(idx) = val;
+ DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
+ idx, val);
+ break;
+ case FloatRegClass:
+ floatRegFile.reg(idx) = val;
+ DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
+ idx, val);
+ break;
+ case CCRegClass:
+ ccRegFile.reg(idx) = val;
+ DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n",
+ idx, val);
+ break;
+ default:
+ panic("Unsupported register class type %d.", type);
+ }
+ }
+
+ void
+ setReg(PhysRegIdPtr phys_reg, const void *val)
+ {
+ const RegClassType type = phys_reg->classValue();
+ const RegIndex idx = phys_reg->index();
+
+ switch (type) {
+ case IntRegClass:
+ setReg(phys_reg, *(RegVal *)val);
+ break;
+ case FloatRegClass:
+ setReg(phys_reg, *(RegVal *)val);
+ break;
+ case VecRegClass:
+ DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
+ idx, *(TheISA::VecRegContainer *)val);
+ vectorRegFile.set(idx, val);
+ break;
+ case VecPredRegClass:
+ DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
+ idx, *(TheISA::VecRegContainer *)val);
+ vecPredRegFile.set(idx, val);
+ break;
+ case CCRegClass:
+ setReg(phys_reg, *(RegVal *)val);
+ break;
+ case VecElemClass:
+ {
+ const auto &elem = *(const TheISA::VecElem *)val;
+ DPRINTF(IEW, "RegFile: Setting element %d of vector
register "
+ "%i to %#x\n", idx, elem);
+ vectorRegFile.reg<TheISA::VecRegContainer>(idx).
+ as<TheISA::VecElem>()[phys_reg->elemIndex()] = elem;
+ }
+ break;
+ default:
+ panic("Unrecognized register class type %d.", type);
+ }
+ }
+
/** Reads an integer register. */
RegVal
readIntReg(PhysRegIdPtr phys_reg) const
diff --git a/src/cpu/o3/thread_context.cc b/src/cpu/o3/thread_context.cc
index 0fbdf67..7acdc96 100644
--- a/src/cpu/o3/thread_context.cc
+++ b/src/cpu/o3/thread_context.cc
@@ -200,6 +200,32 @@
return cpu->readArchCCReg(reg_idx, thread->threadId());
}
+RegVal
+ThreadContext::getRegFlat(const RegId ®) const
+{
+ return cpu->getArchReg(reg, thread->threadId());
+}
+
+void
+ThreadContext::getRegFlat(const RegId ®, void *val) const
+{
+ cpu->getArchReg(reg, val, thread->threadId());
+}
+
+void
+ThreadContext::setRegFlat(const RegId ®, RegVal val)
+{
+ cpu->setArchReg(reg, val, thread->threadId());
+ conditionalSquash();
+}
+
+void
+ThreadContext::setRegFlat(const RegId ®, const void *val)
+{
+ cpu->setArchReg(reg, val, thread->threadId());
+ conditionalSquash();
+}
+
void
ThreadContext::setIntRegFlat(RegIndex reg_idx, RegVal val)
{
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 85cf355..9d40539 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -354,6 +354,12 @@
cpu->squashFromTC(thread->threadId());
}
+ RegVal getRegFlat(const RegId ®) const override;
+ void getRegFlat(const RegId ®, void *val) const override;
+
+ void setRegFlat(const RegId ®, RegVal val) override;
+ void setRegFlat(const RegId ®, const void *val) override;
+
RegVal readIntRegFlat(RegIndex idx) const override;
void setIntRegFlat(RegIndex idx, RegVal val) override;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49109
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3f0bf1e75a5191be98c79fede5aad854a920e9c9
Gerrit-Change-Number: 49109
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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