Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49431 )
Change subject: arch-riscv,dev: Explicitly set num CPUs on platform
......................................................................
arch-riscv,dev: Explicitly set num CPUs on platform
Previously, the RISC-V devices queried the system object in
SimObject::init() for the number of CPUs and the number of threads.
However, the system object doesn't actually count the number of
CPUs/threads until it runs init(). Therefore, we've just been getting
lucky in the order that the SimObject init() functions were called.
This change instead decouples these two functions and makes the number
of CPUs/threads a parameter for the RISC-V interrupt devices. This
change also updates the example config script.
Change-Id: Ic4da5604156837cfeec05e58d188b42a02420de1
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M configs/example/riscv/fs_linux.py
M src/dev/riscv/Clint.py
M src/dev/riscv/HiFive.py
M src/dev/riscv/Plic.py
M src/dev/riscv/clint.cc
M src/dev/riscv/plic.cc
6 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/configs/example/riscv/fs_linux.py
b/configs/example/riscv/fs_linux.py
index 55097ba..982dfa4 100644
--- a/configs/example/riscv/fs_linux.py
+++ b/configs/example/riscv/fs_linux.py
@@ -185,6 +185,7 @@
system.platform.attachOnChipIO(system.membus)
system.platform.attachOffChipIO(system.iobus)
system.platform.attachPlic()
+system.platform.setNumCores(np)
# ---------------------------- Default Setup --------------------------- #
diff --git a/src/dev/riscv/Clint.py b/src/dev/riscv/Clint.py
index 75c89aa..70ec0ed 100644
--- a/src/dev/riscv/Clint.py
+++ b/src/dev/riscv/Clint.py
@@ -52,6 +52,7 @@
cxx_class = 'gem5::Clint'
int_pin = IntSinkPin('Pin to receive RTC signal')
pio_size = Param.Addr(0xC000, "PIO Size")
+ num_threads = Param.Int("Number of threads in the system.")
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, "clint",
self.pio_addr,
diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py
index 8af2ddd..d945590 100755
--- a/src/dev/riscv/HiFive.py
+++ b/src/dev/riscv/HiFive.py
@@ -112,9 +112,6 @@
uart_int_id = Param.Int(0xa, "PLIC Uart interrupt ID")
terminal = Terminal()
- # Dummy param for generating devicetree
- cpu_count = Param.Int(0, "dummy")
-
def _on_chip_devices(self):
"""Returns a list of on-chip peripherals
"""
@@ -172,6 +169,13 @@
for device in self._off_chip_devices():
device.pio = bus.mem_side_ports
+ def setNumCores(self, num_cpu):
+ """ Sets the PLIC and CLINT to have the right number of threads and
+ contexts. Assumes that the cores have a single hardware thread.
+ """
+ self.plic.n_contexts = num_cpu * 2
+ self.clint.num_threads = num_cpu
+
def generateDeviceTree(self, state):
cpus_node = FdtNode("cpus")
cpus_node.append(FdtPropertyWords("timebase-frequency",
[10000000]))
@@ -189,6 +193,8 @@
yield node
+ # For generating devicetree
+ _cpu_count = 0
def annotateCpuDeviceNode(self, cpu, state):
cpu.append(FdtPropertyStrings('mmu-type', 'riscv,sv48'))
cpu.append(FdtPropertyStrings('status', 'okay'))
@@ -202,8 +208,8 @@
int_node.appendCompatible("riscv,cpu-intc")
cpus = self.system.unproxy(self).cpu
- phandle = int_state.phandle(cpus[self.cpu_count])
- self.cpu_count += 1
+ phandle = int_state.phandle(cpus[self._cpu_count])
+ self._cpu_count += 1
int_node.append(FdtPropertyWords("phandle", [phandle]))
cpu.append(int_node)
diff --git a/src/dev/riscv/Plic.py b/src/dev/riscv/Plic.py
index 24ed5a5..be0b629 100644
--- a/src/dev/riscv/Plic.py
+++ b/src/dev/riscv/Plic.py
@@ -51,6 +51,8 @@
cxx_class = 'gem5::Plic'
pio_size = Param.Addr(0x4000000, "PIO Size")
n_src = Param.Int("Number of interrupt sources")
+ n_contexts = Param.Int("Number of interrupt contexts. Usually the
number "
+ "of threads * 2. One for M mode, one for S
mode")
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, "plic",
self.pio_addr,
diff --git a/src/dev/riscv/clint.cc b/src/dev/riscv/clint.cc
index 0356af0..b27b9bf 100644
--- a/src/dev/riscv/clint.cc
+++ b/src/dev/riscv/clint.cc
@@ -52,6 +52,7 @@
Clint::Clint(const Params ¶ms) :
BasicPioDevice(params, params.pio_size),
system(params.system),
+ nThread(params.num_threads),
signal(params.name + ".signal", 0, this),
registers(params.name + ".registers", params.pio_addr, this)
{
@@ -194,7 +195,6 @@
void
Clint::init()
{
- nThread = system->threads.size();
registers.init();
BasicPioDevice::init();
}
diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
index 4dea475..b8f765a 100644
--- a/src/dev/riscv/plic.cc
+++ b/src/dev/riscv/plic.cc
@@ -56,6 +56,7 @@
BasicPioDevice(params, params.pio_size),
system(params.system),
nSrc(params.n_src),
+ nContext(params.n_contexts),
registers(params.name, pioAddr, this),
update([this]{updateOutput();}, name() + ".update")
{
@@ -163,8 +164,6 @@
void
Plic::init()
{
- // Number of contexts
- nContext = system->threads.size() * 2;
// Number of 32-bit pending registesrs where
// each bit correspondings to one interrupt source
nSrc32 = divCeil(nSrc, 32);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic4da5604156837cfeec05e58d188b42a02420de1
Gerrit-Change-Number: 49431
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power <power...@gmail.com>
Gerrit-MessageType: newchange
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