[gem5-dev] Change in gem5/gem5[develop]: arch: Get rid of the is${Type}Reg methods of the Operand class.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49720 )

Change subject: arch: Get rid of the is${Type}Reg methods of the Operand  
class.
......................................................................

arch: Get rid of the is${Type}Reg methods of the Operand class.

These are not used, and would prevent creating a truly generic register
operand class.

Change-Id: Ibffadc7a682b878aee8e632a0f85c06e91a60614
---
M src/arch/isa_parser/operand_types.py
1 file changed, 0 insertions(+), 39 deletions(-)



diff --git a/src/arch/isa_parser/operand_types.py  
b/src/arch/isa_parser/operand_types.py
index f93579b..4b269d4 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -122,27 +122,6 @@
     def isReg(self):
         return 0

-    def isFloatReg(self):
-        return 0
-
-    def isIntReg(self):
-        return 0
-
-    def isCCReg(self):
-        return 0
-
-    def isControlReg(self):
-        return 0
-
-    def isVecReg(self):
-        return 0
-
-    def isVecElem(self):
-        return 0
-
-    def isVecPredReg(self):
-        return 0
-
     def isPCState(self):
         return 0

@@ -177,9 +156,6 @@
 class IntRegOperand(RegOperand):
     reg_class = 'IntRegClass'

-    def isIntReg(self):
-        return 1
-
     def makeConstructor(self, predRead, predWrite):
         c_src = ''
         c_dest = ''
@@ -246,9 +222,6 @@
 class FloatRegOperand(RegOperand):
     reg_class = 'FloatRegClass'

-    def isFloatReg(self):
-        return 1
-
     def makeConstructor(self, predRead, predWrite):
         c_src = ''
         c_dest = ''
@@ -310,9 +283,6 @@
         Operand.__init__(self, parser, full_name, ext, is_src, is_dest)
         self.elemExt = None

-    def isVecReg(self):
-        return 1
-
     def makeDeclElem(self, elem_op):
         (elem_name, elem_ext) = elem_op
         (elem_spec, dflt_elem_ext) = self.elems[elem_name]
@@ -450,9 +420,6 @@
 class VecElemOperand(RegOperand):
     reg_class = 'VecElemClass'

-    def isVecElem(self):
-        return 1
-
     def makeDecl(self):
         if self.is_dest and not self.is_src:
             return '\n\t%s %s;' % (self.ctype, self.base_name)
@@ -486,9 +453,6 @@
 class VecPredRegOperand(RegOperand):
     reg_class = 'VecPredRegClass'

-    def isVecPredReg(self):
-        return 1
-
     def makeDecl(self):
         return ''

@@ -563,9 +527,6 @@
 class CCRegOperand(RegOperand):
     reg_class = 'CCRegClass'

-    def isCCReg(self):
-        return 1
-
     def makeConstructor(self, predRead, predWrite):
         c_src = ''
         c_dest = ''

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibffadc7a682b878aee8e632a0f85c06e91a60614
Gerrit-Change-Number: 49720
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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