Yu-hsin Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49651 )
Change subject: fastmodel: export CortexR52 reset and halt signals
......................................................................
fastmodel: export CortexR52 reset and halt signals
Change-Id: I44a26bad1a91009dbef586ab5d8eeee60352d51e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49651
Reviewed-by: Earl Ou <shunhsin...@google.com>
Reviewed-by: Gabe Black <gabe.bl...@gmail.com>
Maintainer: Gabe Black <gabe.bl...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
M src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
M src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
M src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
8 files changed, 69 insertions(+), 5 deletions(-)
Approvals:
Earl Ou: Looks good to me, approved
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
index 6530854..710584d 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -30,7 +30,7 @@
from m5.objects.ArmInterrupts import ArmInterrupts
from m5.objects.ArmISA import ArmISA
from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
-from m5.objects.IntPin import VectorIntSinkPin
+from m5.objects.IntPin import IntSinkPin, VectorIntSinkPin
from m5.objects.Iris import IrisBaseCPU
from m5.objects.SystemC import SystemC_ScModule
@@ -46,6 +46,11 @@
llpp = AmbaInitiatorSocket(64, 'Low Latency Peripheral Port')
flash = AmbaInitiatorSocket(64, 'Flash')
amba = AmbaInitiatorSocket(64, 'AMBA initiator socket')
+ core_reset = IntSinkPin('Raising this signal will put the core into ' \
+ 'reset mode.')
+ poweron_reset = IntSinkPin('Power on reset. Initializes all the ' \
+ 'processor logic, including debug logic.')
+ halt = IntSinkPin('Raising this signal will put the core into halt
mode.')
CFGEND = Param.Bool(False, "Endianness configuration at reset. 0, " \
"little endian. 1, big endian.")
@@ -108,6 +113,7 @@
spi = VectorIntSinkPin('SPI inputs (0-959)')
ext_slave = AmbaTargetSocket(64, 'AMBA target socket')
+ top_reset = IntSinkPin('This signal resets timer and interrupt
controller.')
CLUSTER_ID = Param.UInt16(0, "CLUSTER_ID[15:8] equivalent to " \
"CFGMPIDRAFF2, CLUSTER_ID[7:0] equivalent to CFGMPIDRAFF1")
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
index 35e4e07..f5817f9 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -86,7 +86,9 @@
// Since PPIs are indexed both by core and by number, modify the
name
// to hold the core number.
return evs->gem5_getPort(csprintf("%s_%d", if_name, num), idx);
- } else if (if_name == "amba" || if_name == "llpp" || if_name
== "flash") {
+ } else if (if_name == "amba" || if_name == "llpp" || if_name
== "flash" ||
+ if_name == "core_reset" || if_name == "poweron_reset" ||
+ if_name == "halt") {
// Since these ports are scalar per core, use the core number as
the
// index. Also verify that that index is not being used.
assert(idx == InvalidPortID);
@@ -150,7 +152,7 @@
{
if (if_name == "spi") {
return evs->gem5_getPort(if_name, idx);
- } else if (if_name == "ext_slave") {
+ } else if (if_name == "ext_slave" || if_name == "top_reset") {
assert(idx == InvalidPortID);
return evs->gem5_getPort(if_name, idx);
} else {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc
b/src/arch/arm/fastmodel/CortexR52/evs.cc
index f4e091e..7f992f2 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -68,12 +68,18 @@
evs(_evs), cpu(_cpu),
llpp(evs->llpp[cpu], name + ".llpp", -1),
flash(evs->flash[cpu], name + ".flash", -1),
- amba(evs->amba[cpu], name + ".amba", -1)
+ amba(evs->amba[cpu], name + ".amba", -1),
+ core_reset(name + ".core_reset", 0),
+ poweron_reset(name + ".poweron_reset", 0),
+ halt(name + ".halt", 0)
{
for (int i = 0; i < Evs::PpiCount; i++) {
ppis.emplace_back(
new CoreInt(csprintf("%s.ppi[%d]", name, i), i, this));
}
+ core_reset.signal_out.bind(evs->core_reset[cpu]);
+ poweron_reset.signal_out.bind(evs->poweron_reset[cpu]);
+ halt.signal_out.bind(evs->halt[cpu]);
}
@@ -82,7 +88,8 @@
const sc_core::sc_module_name &mod_name, const Params &p) :
Base(mod_name),
params(p),
- ext_slave(Base::ext_slave, p.name + ".ext_slave", -1)
+ ext_slave(Base::ext_slave, p.name + ".ext_slave", -1),
+ top_reset(p.name + ".top_reset", 0)
{
for (int i = 0; i < CoreCount; i++)
corePins.emplace_back(new CorePins(this, i));
@@ -92,6 +99,8 @@
new ClstrInt(csprintf("%s.spi[%d]", name(), i), i, this));
}
+ top_reset.signal_out.bind(Base::top_reset);
+
clockRateControl.bind(this->clock_rate_s);
signalInterrupt.bind(this->signal_interrupt);
}
@@ -116,8 +125,16 @@
return this->corePins.at(idx)->flash;
} else if (if_name == "amba") {
return this->corePins.at(idx)->amba;
+ } else if (if_name == "core_reset") {
+ return this->corePins.at(idx)->core_reset;
+ } else if (if_name == "poweron_reset") {
+ return this->corePins.at(idx)->poweron_reset;
+ } else if (if_name == "halt") {
+ return this->corePins.at(idx)->halt;
} else if (if_name == "ext_slave") {
return this->ext_slave;
+ } else if (if_name == "top_reset") {
+ return this->top_reset;
} else if (if_name == "spi") {
return *this->spis.at(idx);
} else if (if_name.substr(0, 3) == "ppi") {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh
b/src/arch/arm/fastmodel/CortexR52/evs.hh
index d0c1253..20870df 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -32,6 +32,7 @@
#include "arch/arm/fastmodel/amba_ports.hh"
#include "arch/arm/fastmodel/common/signal_receiver.hh"
+#include "arch/arm/fastmodel/common/signal_sender.hh"
#include "arch/arm/fastmodel/iris/cpu.hh"
#include "arch/arm/fastmodel/protocol/exported_clock_rate_control.hh"
#include "arch/arm/fastmodel/protocol/signal_interrupt.hh"
@@ -102,6 +103,10 @@
AmbaInitiator llpp;
AmbaInitiator flash;
AmbaInitiator amba;
+
+ SignalSender core_reset;
+ SignalSender poweron_reset;
+ SignalSender halt;
};
std::vector<std::unique_ptr<CorePins>> corePins;
@@ -116,6 +121,8 @@
AmbaTarget ext_slave;
+ SignalSender top_reset;
+
public:
ScxEvsCortexR52(const Params &p) : ScxEvsCortexR52(p.name.c_str(), p)
{}
ScxEvsCortexR52(const sc_core::sc_module_name &mod_name, const Params
&p);
diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
index 720d66f..a15fe74 100644
--- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
@@ -45,6 +45,10 @@
core.flash_m => self.flash;
core.pvbus_core_m => self.amba;
self.ext_slave => core.ext_slave_s;
+ self.core_reset => core.reset;
+ self.poweron_reset => core.cpuporeset;
+ self.top_reset => core.topreset;
+ self.halt => core.cpuhalt;
// Clocks.
clock1Hz.clk_out => clockDiv.clk_in;
@@ -66,6 +70,10 @@
master port<PVBus> flash[1];
master port<PVBus> amba[1];
slave port<PVBus> ext_slave;
+ slave port<Signal> core_reset[1];
+ slave port<Signal> poweron_reset[1];
+ slave port<Signal> halt[1];
+ slave port<Signal> top_reset;
slave port<ExportedClockRateControl> clock_rate_s
{
diff --git a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
index bcbf1f4..9b992a4 100644
--- a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
@@ -45,6 +45,10 @@
core.flash_m => self.flash;
core.pvbus_core_m => self.amba;
self.ext_slave => core.ext_slave_s;
+ self.core_reset => core.reset;
+ self.poweron_reset => core.cpuporeset;
+ self.top_reset => core.topreset;
+ self.halt => core.cpuhalt;
// Clocks.
clock1Hz.clk_out => clockDiv.clk_in;
@@ -67,6 +71,10 @@
master port<PVBus> flash[2];
master port<PVBus> amba[2];
slave port<PVBus> ext_slave;
+ slave port<Signal> core_reset[2];
+ slave port<Signal> poweron_reset[2];
+ slave port<Signal> halt[2];
+ slave port<Signal> top_reset;
slave port<ExportedClockRateControl> clock_rate_s
{
diff --git a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
index 3d63bbf..18619b9 100644
--- a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
@@ -45,6 +45,10 @@
core.flash_m => self.flash;
core.pvbus_core_m => self.amba;
self.ext_slave => core.ext_slave_s;
+ self.core_reset => core.reset;
+ self.poweron_reset => core.cpuporeset;
+ self.top_reset => core.topreset;
+ self.halt => core.cpuhalt;
// Clocks.
clock1Hz.clk_out => clockDiv.clk_in;
@@ -68,6 +72,10 @@
master port<PVBus> flash[3];
master port<PVBus> amba[3];
slave port<PVBus> ext_slave;
+ slave port<Signal> core_reset[3];
+ slave port<Signal> poweron_reset[3];
+ slave port<Signal> halt[3];
+ slave port<Signal> top_reset;
slave port<ExportedClockRateControl> clock_rate_s
{
diff --git a/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
b/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
index 6443383..d22079f 100644
--- a/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
@@ -45,6 +45,10 @@
core.flash_m => self.flash;
core.pvbus_core_m => self.amba;
self.ext_slave => core.ext_slave_s;
+ self.core_reset => core.reset;
+ self.poweron_reset => core.cpuporeset;
+ self.top_reset => core.topreset;
+ self.halt => core.cpuhalt;
// Clocks.
clock1Hz.clk_out => clockDiv.clk_in;
@@ -69,6 +73,10 @@
master port<PVBus> flash[4];
master port<PVBus> amba[4];
slave port<PVBus> ext_slave;
+ slave port<Signal> core_reset[4];
+ slave port<Signal> poweron_reset[4];
+ slave port<Signal> halt[4];
+ slave port<Signal> top_reset;
slave port<ExportedClockRateControl> clock_rate_s
{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I44a26bad1a91009dbef586ab5d8eeee60352d51e
Gerrit-Change-Number: 49651
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang <yuhsi...@google.com>
Gerrit-Reviewer: Earl Ou <shunhsin...@google.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Yu-hsin Wang <yuhsi...@google.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Han-sheng Liu <handsome...@google.com>
Gerrit-MessageType: merged
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