Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49827 )
Change subject: arch-arm: add size check for AdvSIMD copy
......................................................................
arch-arm: add size check for AdvSIMD copy
imm5_pos and size are the output of findLsbSet. When imm5 is zero,
imm5_pos and size are 64 which will cause assert fail in the following
bits calls. We detect this case and return an Unknown instruction.
Change-Id: I4ed2513267fff5b5bdb81723617ff74fb9f82482
---
M src/arch/arm/isa/formats/neon64.isa
1 file changed, 12 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/isa/formats/neon64.isa
b/src/arch/arm/isa/formats/neon64.isa
index 1948a34..660d118 100644
--- a/src/arch/arm/isa/formats/neon64.isa
+++ b/src/arch/arm/isa/formats/neon64.isa
@@ -1205,6 +1205,9 @@
if (!q || (imm4 & mask(imm5_pos)))
return new Unknown64(machInst);
+ if (imm5_pos > 3)
+ return new Unknown64(machInst);
+
index1 = bits(imm5, 4, imm5_pos + 1); // dst
index2 = bits(imm4, 3, imm5_pos); // src
@@ -1224,6 +1227,9 @@
switch (imm4) {
case 0x0:
+ if (imm5_pos > 3)
+ return new Unknown64(machInst);
+
index1 = bits(imm5, 4, imm5_pos + 1);
switch (imm5_pos) {
case 0:
@@ -1289,6 +1295,9 @@
return new Unknown64(machInst);
}
case 0x5:
+ if (imm5_pos > 3)
+ return new Unknown64(machInst);
+
index1 = bits(imm5, 4, imm5_pos + 1);
switch (imm5_pos) {
case 0:
@@ -2431,6 +2440,9 @@
IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
uint8_t size = findLsbSet(imm5);
+ if (size > 3)
+ return new Unknown64(machInst);
+
uint8_t index = bits(imm5, 4, size + 1);
return decodeNeonUTwoShiftUReg<DupElemScX>(
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4ed2513267fff5b5bdb81723617ff74fb9f82482
Gerrit-Change-Number: 49827
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang <yuhsi...@google.com>
Gerrit-MessageType: newchange
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