Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49887 )
Change subject: arch: Ensure using namespace * doesn't leak from generated
ISA files.
......................................................................
arch: Ensure using namespace * doesn't leak from generated ISA files.
Only use "using namespace" with the *ISAInst namespace, not the top
level namespace. Also only using namespace *ISA, and not the gem5
namespace itself. The *ISAInst namespace is already in the gem5
namespace, and so will resolve names in it automatically.
Change-Id: Iebf3c9519c65baba073d73744665f8c98880804c
---
M src/arch/arm/isa/includes.isa
M src/arch/mips/isa/includes.isa
M src/arch/power/isa/includes.isa
M src/arch/riscv/isa/includes.isa
M src/arch/sparc/isa/includes.isa
M src/arch/x86/isa/includes.isa
6 files changed, 45 insertions(+), 30 deletions(-)
diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index 3ec3e65..c01eb72 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -70,13 +70,10 @@
#include "mem/packet.hh"
#include "sim/faults.hh"
-namespace gem5
-{
-namespace ArmISAInst
+namespace gem5::ArmISAInst
{
using namespace ArmISA;
-} // namespace ArmISAInst
-} // namespace gem5
+} // namespace gem5::ArmISAInst
}};
@@ -94,8 +91,10 @@
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
-using namespace gem5;
+namespace gem5::ArmISAInst
+{
using namespace ArmISA;
+} // namespace gem5::ArmISAInst
}};
output exec {{
@@ -120,7 +119,9 @@
#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
-using namespace gem5;
+namespace gem5::ArmISAInst
+{
using namespace ArmISA;
+} // namespace gem5::ArmISAInst
}};
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 6802810..df9a4ce 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -64,8 +64,10 @@
#include "mem/packet.hh"
#include "sim/full_system.hh"
-using namespace gem5;
+namespace gem5::MipsISAInst
+{
using namespace MipsISA;
+} // namespace gem5::MipsISAInst
}};
output exec {{
@@ -96,7 +98,8 @@
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
-using namespace gem5;
+namespace gem5::MipsISAInst
+{
using namespace MipsISA;
+} // namespace gem5::MipsISAInst
}};
-
diff --git a/src/arch/power/isa/includes.isa
b/src/arch/power/isa/includes.isa
index e9b950b..5ab9e89 100644
--- a/src/arch/power/isa/includes.isa
+++ b/src/arch/power/isa/includes.isa
@@ -46,8 +46,10 @@
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
-using namespace gem5;
+namespace gem5::PowerISAInst
+{
using namespace PowerISA;
+} // namespace gem5::PowerISAInst
}};
output decoder {{
@@ -60,8 +62,10 @@
#include "base/cprintf.hh"
#include "cpu/thread_context.hh"
-using namespace gem5;
+namespace gem5::PowerISAInst
+{
using namespace PowerISA;
+} // namespace gem5::PowerISAInst
}};
output exec {{
@@ -78,7 +82,8 @@
#include "mem/packet_access.hh"
#include "sim/sim_exit.hh"
-using namespace gem5;
+namespace gem5::PowerISAInst
+{
using namespace PowerISA;
+} // namespace gem5::PowerISAInst
}};
-
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index 6ffa277..88837e5 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -74,8 +74,10 @@
#include "mem/request.hh"
#include "sim/full_system.hh"
-using namespace gem5;
+namespace gem5::RiscvISAInst
+{
using namespace RiscvISA;
+} // namespace gem5::RiscvISAInst
}};
output exec {{
@@ -106,6 +108,8 @@
#include "sim/sim_exit.hh"
#include "sim/system.hh"
-using namespace gem5;
+namespace gem5::RiscvISAInst
+{
using namespace RiscvISA;
+} // namespace gem5::RiscvISAInst
}};
diff --git a/src/arch/sparc/isa/includes.isa
b/src/arch/sparc/isa/includes.isa
index c561056..d35619d 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -66,8 +66,10 @@
#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh"
-using namespace gem5;
+namespace gem5::SparcISAInst
+{
using namespace SparcISA;
+} // namespace gem5::SparcISAInst
}};
output exec {{
@@ -87,7 +89,8 @@
#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
-using namespace gem5;
+namespace gem5::SparcISAInst
+{
using namespace SparcISA;
+} // namespace gem5::SparcISAInst
}};
-
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index fe28516e..bb07405 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -69,14 +69,10 @@
#include "mem/packet.hh"
#include "sim/faults.hh"
-using namespace gem5;
-using X86ISA::GpRegIndex;
-using X86ISA::FpRegIndex;
-using X86ISA::CtrlRegIndex;
-using X86ISA::CrRegIndex;
-using X86ISA::DbgRegIndex;
-using X86ISA::SegRegIndex;
-
+namespace gem5::X86ISAInst
+{
+using namespace X86ISA;
+} // namespace gem5::X86ISAInst
}};
output decoder {{
@@ -97,8 +93,10 @@
#include "mem/packet.hh"
#include "sim/full_system.hh"
-using namespace gem5;
+namespace gem5::X86ISAInst
+{
using namespace X86ISA;
+} // namespace gem5::X86ISAInst
}};
output exec {{
@@ -125,7 +123,8 @@
#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
-using namespace gem5;
+namespace gem5::X86ISAInst
+{
using namespace X86ISA;
+} // namespace gem5::X86ISAInst
}};
-
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49887
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iebf3c9519c65baba073d73744665f8c98880804c
Gerrit-Change-Number: 49887
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
