Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50249 )
Change subject: arch-arm,cpu: Simplify the RegClass constructor(s).
......................................................................
arch-arm,cpu: Simplify the RegClass constructor(s).
Replace the two constructors with one that takes the truly mandantory
parameters, and then a function to derive a new RegClass with some sort
of adjustment, currently by adding custom ops, or setting a non-standard
register size.
Because the constructor and the modifier function are constexpr, they
should fold away and not actually create extra temporary copies of the
RegClass in the modifier functions.
Change-Id: I8acb755eb28fc8474ec453c51ad205a52eed9a8e
---
M src/arch/arm/regs/misc.hh
M src/arch/arm/regs/vec.hh
M src/cpu/reg_class.hh
3 files changed, 34 insertions(+), 18 deletions(-)
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index c2127b2..969e284 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -2200,8 +2200,9 @@
static inline MiscRegClassOps miscRegClassOps;
- inline constexpr RegClass miscRegClass(MiscRegClass, NUM_MISCREGS,
- miscRegClassOps, debug::MiscRegs);
+ inline constexpr RegClass miscRegClass =
+ RegClass(MiscRegClass, NUM_MISCREGS, debug::MiscRegs).
+ ops(miscRegClassOps);
// This mask selects bits of the CPSR that actually go in the CondCodes
// integer register to allow renaming.
diff --git a/src/arch/arm/regs/vec.hh b/src/arch/arm/regs/vec.hh
index fcb9375..45eac30 100644
--- a/src/arch/arm/regs/vec.hh
+++ b/src/arch/arm/regs/vec.hh
@@ -98,12 +98,17 @@
static inline TypedRegClassOps<ArmISA::VecRegContainer> vecRegClassOps;
static inline TypedRegClassOps<ArmISA::VecPredRegContainer>
vecPredRegClassOps;
-inline constexpr RegClass vecRegClass(VecRegClass, NumVecRegs,
vecRegClassOps,
- debug::VecRegs, sizeof(VecRegContainer));
-inline constexpr RegClass vecElemClass(VecElemClass,
- NumVecRegs * NumVecElemPerVecReg, vecRegElemClassOps,
debug::VecRegs);
-inline constexpr RegClass vecPredRegClass(VecPredRegClass, NumVecPredRegs,
- vecPredRegClassOps, debug::VecPredRegs,
sizeof(VecPredRegContainer));
+inline constexpr RegClass vecRegClass =
+ RegClass(VecRegClass, NumVecRegs, debug::VecRegs).
+ ops(vecRegClassOps).
+ regType<VecRegContainer>();
+inline constexpr RegClass vecElemClass =
+ RegClass(VecElemClass, NumVecRegs * NumVecElemPerVecReg,
debug::VecRegs).
+ ops(vecRegElemClassOps);
+inline constexpr RegClass vecPredRegClass =
+ RegClass(VecPredRegClass, NumVecPredRegs, debug::VecPredRegs).
+ ops(vecPredRegClassOps).
+ regType<VecPredRegContainer>();
} // namespace ArmISA
} // namespace gem5
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 58251c5..cfc86ee 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -88,11 +88,11 @@
RegClassType _type;
size_t _size;
- size_t _regBytes;
+ size_t _regBytes = sizeof(RegVal);
// This is how much to shift an index by to get an offset of a
register in
// a register file from the register index, which would otherwise need
to
// be calculated with a multiply.
- size_t _regShift;
+ size_t _regShift = ceilLog2(sizeof(RegVal));
static inline RegClassOps defaultOps;
RegClassOps *_ops = &defaultOps;
@@ -100,16 +100,26 @@
public:
constexpr RegClass(RegClassType type, size_t new_size,
- const debug::Flag &debug_flag, size_t
reg_bytes=sizeof(RegVal)) :
- _type(type), _size(new_size), _regBytes(reg_bytes),
- _regShift(ceilLog2(reg_bytes)), debugFlag(debug_flag)
+ const debug::Flag &debug_flag) :
+ _type(type), _size(new_size), debugFlag(debug_flag)
{}
- constexpr RegClass(RegClassType type, size_t new_size,
- RegClassOps &new_ops, const debug::Flag &debug_flag,
- size_t reg_bytes=sizeof(RegVal)) :
- RegClass(type, new_size, debug_flag, reg_bytes)
+
+ constexpr RegClass
+ ops(RegClassOps &new_ops) const
{
- _ops = &new_ops;
+ RegClass reg_class = *this;
+ reg_class._ops = &new_ops;
+ return reg_class;
+ }
+
+ template <class RegType>
+ constexpr RegClass
+ regType() const
+ {
+ RegClass reg_class = *this;
+ reg_class._regBytes = sizeof(RegType);
+ reg_class._regShift = ceilLog2(reg_class._regBytes);
+ return reg_class;
}
constexpr RegClassType type() const { return _type; }
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8acb755eb28fc8474ec453c51ad205a52eed9a8e
Gerrit-Change-Number: 50249
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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