Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50508 )
Change subject: arch-arm: Syncronize GIC CPU interface when changing EL
......................................................................
arch-arm: Syncronize GIC CPU interface when changing EL
From the GIC architecture specification (ihi0069) [1]
"The assertion and de-assertion of IRQs and FIQs are affected by the
current Exception level and Security state of the PE. As part of the
Context Synchronization that occurs as the result of taking or returning
from an exception, the CPU interface ensures that IRQ and FIQ are both
appropriately asserted or deasserted for the Exception level and
Security state that the PE is entering."
[1]: https://developer.arm.com/documentation/ihi0069/latest
Change-Id: I10444a3aad5c06aabc13e1cbd70a32192531a31d
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/isa.cc
M src/dev/arm/gic_v3_cpu_interface.hh
2 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 51856ca..8d5addc 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -905,13 +905,12 @@
CPSR old_cpsr = miscRegs[MISCREG_CPSR];
int old_mode = old_cpsr.mode;
CPSR cpsr = val;
- if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
- getMMUPtr(tc)->invalidateMiscReg();
- }
-
if (cpsr.pan != old_cpsr.pan) {
getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
}
+ if (cpsr.il != old_cpsr.il) {
+ getMMUPtr(tc)->invalidateMiscReg();
+ }
DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d
mode:%#x\n",
miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a,
cpsr.mode);
@@ -931,6 +930,24 @@
} else {
tc->pcState(pc);
}
+
+ setMiscRegNoEffect(misc_reg, newVal);
+
+ if (old_mode != cpsr.mode) {
+ getMMUPtr(tc)->invalidateMiscReg();
+ if (gicv3CpuInterface) {
+ // The assertion and de-assertion of IRQs and FIQs are
+ // affected by the current Exception level and Security
+ // state of the PE. As part of the Context
+ // Synchronization that occurs as the result of taking
+ // or returning from an exception, the CPU interface
+ // ensures that IRQ and FIQ are both appropriately
+ // asserted or deasserted for the Exception level and
+ // Security state that the PE is entering.
+ static_cast<Gicv3CPUInterface&>(
+ getGICv3CPUInterface()).update();
+ }
+ }
} else {
#ifndef NDEBUG
if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
@@ -2333,8 +2350,8 @@
tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7)
- 1);
break;
}
+ setMiscRegNoEffect(misc_reg, newVal);
}
- setMiscRegNoEffect(misc_reg, newVal);
}
BaseISADevice &
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh
b/src/dev/arm/gic_v3_cpu_interface.hh
index 9f60d84..7058d66 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -50,12 +50,18 @@
class Gicv3Distributor;
class Gicv3Redistributor;
+namespace ArmISA
+{
+class ISA;
+}
+
class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
{
private:
friend class Gicv3Distributor;
friend class Gicv3Redistributor;
+ friend class ArmISA::ISA;
protected:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I10444a3aad5c06aabc13e1cbd70a32192531a31d
Gerrit-Change-Number: 50508
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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