Austin Harris has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/51452 )

Change subject: python: Fix L1 data cache size in cache components
......................................................................

python: Fix L1 data cache size in cache components

Change-Id: I96119e2a002de3904e87625a3de89abb3cc724a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51452
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
Maintainer: Jason Lowe-Power <power...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py M src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
2 files changed, 15 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
index 03150da..ce04f46 100644
--- a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
@@ -102,7 +102,7 @@
         ]

         self.l1dcaches = [
-            L1DCache(size=self._l1i_size)
+            L1DCache(size=self._l1d_size)
             for i in range(board.get_processor().get_num_cores())
         ]
         # ITLB Page walk caches
diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
index eb4dae1..cd55c6e 100644
--- a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
@@ -127,7 +127,7 @@
             for i in range(board.get_processor().get_num_cores())
         ]
         self.l1dcaches = [
-            L1DCache(size=self._l1i_size)
+            L1DCache(size=self._l1d_size)
             for i in range(board.get_processor().get_num_cores())
         ]
         self.l2buses = [

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I96119e2a002de3904e87625a3de89abb3cc724a9
Gerrit-Change-Number: 51452
Gerrit-PatchSet: 2
Gerrit-Owner: Austin Harris <m...@austin-harris.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Austin Harris <m...@austin-harris.com>
Gerrit-Reviewer: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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