Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51928 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-ruby: Add GPUonly parameter for VIPER
......................................................................
mem-ruby: Add GPUonly parameter for VIPER
Currently MOESI_AMD_Base used in VIPER has a CPUonly parameter which
indicates that messages should not try to add GPU SLICC controllers as
destinations. This adds the analogue GPUonly parameter which indicates
that requests should not try to add CPU SLICC controllers.
Also adds an assert to ensure the outgoing message has at least one
destination. This assert would indicate a misconfiguration.
Change-Id: Ibb0affd4606084fca021f0e7c117d4ff8c06d429
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51928
Tested-by: kokoro <noreply+kok...@google.com>
Maintainer: Matt Sinclair <mattdsincl...@gmail.com>
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
Reviewed-by: Matt Sinclair <mattdsincl...@gmail.com>
---
M src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
1 file changed, 46 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
index a99ac53..d176581 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
@@ -38,6 +38,7 @@
Cycles l3_hit_latency := 50;
bool noTCCdir := "False";
bool CPUonly := "False";
+ bool GPUonly := "False";
int TCC_select_num_bits;
bool useL3OnWT := "False";
Cycles to_memory_controller_latency := 1;
@@ -652,7 +653,9 @@
out_msg.Type := ProbeRequestType:PrbInv;
out_msg.ReturnData := true;
out_msg.MessageSize := MessageSizeType:Control;
- out_msg.Destination.broadcast(MachineType:CorePair);
+ if (!GPUonly) {
+ out_msg.Destination.broadcast(MachineType:CorePair);
+ }
// Add relevant TCC node to list. This replaces all TCPs and SQCs
if (CPUonly) {
@@ -677,6 +680,7 @@
APPEND_TRANSITION_COMMENT(" dc: Acks remaining: ");
APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
tbe.ProbeRequestStartTime := curCycle();
+ assert(out_msg.Destination.count() > 0);
}
}
}
@@ -688,7 +692,10 @@
out_msg.Type := ProbeRequestType:PrbInv;
out_msg.ReturnData := true;
out_msg.MessageSize := MessageSizeType:Control;
- out_msg.Destination.broadcast(MachineType:CorePair); // won't be
realistic for multisocket
+ if (!GPUonly) {
+ // won't be realistic for multisocket
+ out_msg.Destination.broadcast(MachineType:CorePair);
+ }
// add relevant TCC node to list. This replaces all TCPs and SQCs
if (((in_msg.Type == CoherenceRequestType:WriteThrough ||
@@ -715,6 +722,7 @@
APPEND_TRANSITION_COMMENT(" dc: Acks remaining: ");
APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
tbe.ProbeRequestStartTime := curCycle();
+ assert(out_msg.Destination.count() > 0);
}
}
}
@@ -726,7 +734,9 @@
out_msg.Type := ProbeRequestType:PrbDowngrade;
out_msg.ReturnData := true;
out_msg.MessageSize := MessageSizeType:Control;
- out_msg.Destination.broadcast(MachineType:CorePair);
+ if (!GPUonly) {
+ out_msg.Destination.broadcast(MachineType:CorePair);
+ }
// add relevant TCC node to the list. This replaces all TCPs and
SQCs
if (noTCCdir || CPUonly) {
//Don't need to notify TCC about reads
@@ -751,6 +761,7 @@
APPEND_TRANSITION_COMMENT(" sc: Acks remaining: ");
APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
tbe.ProbeRequestStartTime := curCycle();
+ assert(out_msg.Destination.count() > 0);
}
}
}
@@ -762,7 +773,10 @@
out_msg.Type := ProbeRequestType:PrbDowngrade;
out_msg.ReturnData := true;
out_msg.MessageSize := MessageSizeType:Control;
- out_msg.Destination.broadcast(MachineType:CorePair); // won't be
realistic for multisocket
+ if (!GPUonly) {
+ // won't be realistic for multisocket
+ out_msg.Destination.broadcast(MachineType:CorePair);
+ }
// add relevant TCC node to the list. This replaces all TCPs and
SQCs
if (noTCCdir || CPUonly) {
//Don't need to notify TCC about reads
@@ -788,6 +802,7 @@
APPEND_TRANSITION_COMMENT(" sc: Acks remaining: ");
APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
tbe.ProbeRequestStartTime := curCycle();
+ assert(out_msg.Destination.count() > 0);
}
}
}
@@ -799,7 +814,10 @@
out_msg.Type := ProbeRequestType:PrbInv;
out_msg.ReturnData := false;
out_msg.MessageSize := MessageSizeType:Control;
- out_msg.Destination.broadcast(MachineType:CorePair); // won't be
realistic for multisocket
+ if (!GPUonly) {
+ // won't be realistic for multisocket
+ out_msg.Destination.broadcast(MachineType:CorePair);
+ }
// add relevant TCC node to the list. This replaces all TCPs and
SQCs
if (noTCCdir && !CPUonly) {
@@ -825,6 +843,7 @@
APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
DPRINTF(RubySlicc, "%s\n", out_msg);
tbe.ProbeRequestStartTime := curCycle();
+ assert(out_msg.Destination.count() > 0);
}
}
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibb0affd4606084fca021f0e7c117d4ff8c06d429
Gerrit-Change-Number: 51928
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Kyle Roarty <kyleroarty1...@gmail.com>
Gerrit-Reviewer: Matt Sinclair <mattdsincl...@gmail.com>
Gerrit-Reviewer: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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