Mahyar Samani has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51609 )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem: Adding PortTerminator
......................................................................
mem: Adding PortTerminator
This change adds the source code for the PortTerminator SimObject.
It could be used to connect request/response ports in the system
that can not be connected to any other ports. This will prevent
errors caused by orphan ports in the system. As an example if
you have set up a cache hierarchy and do not want to test its
performance in full system mode and want to use PyTrafficGen
instead, your system will end up with an icache or walker ports
that are not connected to anything. In this case, you can use a
PortTerminator to connect the orphan ports in your system.
Change-Id: I5e19cdd3ce064638ffabf29d29225eda77ffc146
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51609
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
Maintainer: Jason Lowe-Power <power...@gmail.com>
---
A src/mem/PortTerminator.py
A src/mem/port_terminator.cc
A src/mem/port_terminator.hh
M src/mem/SConscript
4 files changed, 239 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/PortTerminator.py b/src/mem/PortTerminator.py
new file mode 100644
index 0000000..761f5ed
--- /dev/null
+++ b/src/mem/PortTerminator.py
@@ -0,0 +1,39 @@
+# Copyright (c) 2021 The Regents of the University of California.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+from m5.params import *
+from m5.SimObject import SimObject
+
+class PortTerminator(SimObject):
+ type = 'PortTerminator'
+ cxx_header = "mem/port_terminator.hh"
+ cxx_class = 'gem5::PortTerminator'
+
+ req_ports = VectorRequestPort("Vector port for connecting terminating "
+ "response ports.")
+ resp_ports = VectorResponsePort("Vector port for terminating "
+ "request ports.")
\ No newline at end of file
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 5338b79..ddf6fee 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -58,6 +58,7 @@
SimObject('HMCController.py')
SimObject('SerialLink.py')
SimObject('MemDelay.py')
+SimObject('PortTerminator.py')
Source('abstract_mem.cc')
Source('addr_mapper.cc')
@@ -85,6 +86,7 @@
Source('htm.cc')
Source('serial_link.cc')
Source('mem_delay.cc')
+Source('port_terminator.cc')
GTest('translation_gen.test', 'translation_gen.test.cc')
diff --git a/src/mem/port_terminator.cc b/src/mem/port_terminator.cc
new file mode 100644
index 0000000..57263b4
--- /dev/null
+++ b/src/mem/port_terminator.cc
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2021 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "mem/port_terminator.hh"
+
+namespace gem5 {
+
+PortTerminator::PortTerminator(const PortTerminatorParams ¶ms):
+ SimObject(params)
+{
+ for (int i = 0; i < params.port_req_ports_connection_count; ++i) {
+ reqPorts.emplace_back(name() + ".req_ports" + std::to_string(i),
this);
+ }
+ for (int j = 0; j < params.port_resp_ports_connection_count; ++j) {
+ reqPorts.emplace_back(name() + ".resp_ports" +
+ std::to_string(j), this);
+ }
+}
+
+Port &
+PortTerminator::getPort(const std::string &if_name, PortID idx)
+{
+ if (if_name == "req_ports" && idx < reqPorts.size()) {
+ return reqPorts[idx];
+ } else if (if_name == "resp_ports" && idx < respPorts.size()) {
+ return respPorts[idx];
+ } else {
+ return SimObject::getPort(if_name, idx);
+ }
+}
+
+}
\ No newline at end of file
diff --git a/src/mem/port_terminator.hh b/src/mem/port_terminator.hh
new file mode 100644
index 0000000..233b66d
--- /dev/null
+++ b/src/mem/port_terminator.hh
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2021 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MEM_PORT_TERMINATOR_HH__
+#define __MEM_PORT_TERMINATOR_HH__
+
+/**
+ * @file port_terminator.hh
+ * Contains the description of the class PortTerminator. It is useful for
cases
+ * where you do not need to connect all of the ports in your system, but
the
+ * simulator is complaining about orphan ports. For example if you have
+ * configured a cache hierarchy and want to test its performance using
+ * PyTrafficGen, you will end up with an icache that is not connected to
any
+ * other component in the system. In this case you can just connect that
port
+ * to this object. This object will not issue any request or respond to any
+ * request. It is neccessary to make sure the ports that are connected to
+ * a PortTerminator are never going to be used in your system.
+ */
+
+#include <vector>
+
+#include "mem/port.hh"
+#include "params/PortTerminator.hh"
+#include "sim/sim_object.hh"
+
+namespace gem5
+{
+
+class PortTerminator : public SimObject
+{
+ private:
+ /**
+ * @brief definition of the ReqPort class. It is of type RequestPort
+ * It will always return true when it receives a timing response.
However,
+ * it should never become useful if PortTerminator is used correctly in
+ * your system (since it is a pure virtual function it should be
+ * implemented for any class that inherits from RequestPort). It will
never
+ * send request retires, nor it will need to keep track of address
ranges
+ * of its peer port.
+ */
+ class ReqPort : public RequestPort
+ {
+ public:
+ ReqPort(const std::string &name, PortTerminator *owner):
+ RequestPort(name, owner)
+ {}
+ protected:
+ bool recvTimingResp(PacketPtr pkt) override
+ {
+ panic("Received an unexpected response. RequestPorts on a "
+ "PortTerminator never issue any requests. Therefore, they
should "
+ "never receive a response.\n");
+ }
+
+ void recvReqRetry() override
+ {
+ return;
+ }
+
+ void recvRangeChange() override
+ {
+ return;
+ }
+ };
+
+ /**
+ * @brief definition of the RespPort class. It is of type ResponsePort
+ * It is a ReponsePort that should never receive a request. If this is
not
+ * true in the system you configured, probably you should not use
+ * PortTerminator for the port connected to PortTerminator.
+ */
+ class RespPort : public ResponsePort
+ {
+ public:
+ RespPort(const std::string &name, PortTerminator *owner):
+ ResponsePort(name, owner)
+ {}
+ };
+
+ std::vector<ReqPort> reqPorts;
+
+ std::vector<RespPort> respPorts;
+
+ public:
+ PortTerminator(const PortTerminatorParams ¶ms);
+
+ Port &getPort(const std::string &if_name,
+ PortID idx = InvalidPortID) override;
+};
+
+}
+
+#endif // __MEM_PORT_TERMINATOR_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5e19cdd3ce064638ffabf29d29225eda77ffc146
Gerrit-Change-Number: 51609
Gerrit-PatchSet: 6
Gerrit-Owner: Mahyar Samani <msam...@ucdavis.edu>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Mahyar Samani <msam...@ucdavis.edu>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-MessageType: merged
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