Yu-hsin Wang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/52623 )

Change subject: fastmodel: CortexR52 support gdb
......................................................................

fastmodel: CortexR52 support gdb

We change several things to support basic gdb.

1. Correct the memory translation.
memory_getUsefulAddressTranslations returns an empty list. So there's no
memory translation in R52.

2. Implement FPSCR for gdb collecting status.

3. Correct the breakpoint memory space.

Change-Id: Icc824502faec5ac228003f0de7e9dbe26babe7ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52623
Reviewed-by: Gabe Black <gabe.bl...@gmail.com>
Reviewed-by: Earl Ou <shunhsin...@google.com>
Maintainer: Gabe Black <gabe.bl...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/fastmodel/CortexR52/thread_context.cc
M src/arch/arm/fastmodel/CortexR52/thread_context.hh
2 files changed, 47 insertions(+), 29 deletions(-)

Approvals:
  Earl Ou: Looks good to me, but someone else must approve
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.cc b/src/arch/arm/fastmodel/CortexR52/thread_context.cc
index 0f2dfa0..269baf5 100644
--- a/src/arch/arm/fastmodel/CortexR52/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexR52/thread_context.cc
@@ -49,31 +49,9 @@
 bool
 CortexR52TC::translateAddress(Addr &paddr, Addr vaddr)
 {
-    // Determine what memory spaces are currently active.
-    Iris::CanonicalMsn in_msn;
-    switch (ArmISA::currEL(this)) {
-      case ArmISA::EL3:
-        in_msn = Iris::SecureMonitorMsn;
-        break;
-      case ArmISA::EL2:
-        in_msn = Iris::NsHypMsn;
-        break;
-      default:
-        in_msn = Iris::GuestMsn;
-        break;
-    }
-
-    Iris::CanonicalMsn out_msn = ArmISA::isSecure(this) ?
-        Iris::PhysicalMemorySecureMsn : Iris::PhysicalMemoryNonSecureMsn;
-
-    // Figure out what memory spaces match the canonical numbers we need.
-    iris::MemorySpaceId in = getMemorySpaceId(in_msn);
-    iris::MemorySpaceId out = getMemorySpaceId(out_msn);
-
-    panic_if(in == iris::IRIS_UINT64_MAX || out == iris::IRIS_UINT64_MAX,
-            "Canonical IRIS memory space numbers not found.");
-
-    return ThreadContext::translateAddress(paddr, out, vaddr, in);
+    // No MMU here.
+    paddr = vaddr;
+    return true;
 }

 void
@@ -89,6 +67,23 @@
     extractResourceMap(ccRegIds, resources, ccRegIdxNameMap);
 }

+void
+CortexR52TC::sendFunctional(PacketPtr pkt)
+{
+  auto msn = Iris::PhysicalMemoryMsn;
+  auto id = getMemorySpaceId(msn);
+
+  auto addr = pkt->getAddr();
+  auto size = pkt->getSize();
+  auto data = pkt->getPtr<uint8_t>();
+
+  pkt->makeResponse();
+  if (pkt->isRead())
+      readMem(id, addr, data, size);
+  else
+      writeMem(id, addr, data, size);
+}
+
 RegVal
 CortexR52TC::readIntReg(RegIndex reg_idx) const
 {
@@ -148,9 +143,7 @@
 CortexR52TC::getBpSpaceIds() const
 {
     if (bpSpaceIds.empty()) {
-        std::vector<Iris::CanonicalMsn> msns{
-            Iris::SecureMonitorMsn, Iris::GuestMsn, Iris::NsHypMsn,
-            Iris::HypAppMsn};
+ std::vector<Iris::CanonicalMsn> msns{Iris::GuestMsn, Iris::NsHypMsn};
         for (auto &msn : msns) {
             auto id = getMemorySpaceId(msn);
             if (id != iris::IRIS_UINT64_MAX)
@@ -609,7 +602,7 @@
         // ArmISA::MISCREG_NZCV?
         // ArmISA::MISCREG_DAIF?
         // ArmISA::MISCREG_FPCR?
-        // ArmISA::MISCREG_FPSR?
+        { ArmISA::MISCREG_FPSCR, "FPSCR" },
         // ArmISA::MISCREG_DSPSR_EL0?
         // ArmISA::MISCREG_DLR_EL0?
         // ArmISA::MISCREG_SPSR_EL2?
diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.hh b/src/arch/arm/fastmodel/CortexR52/thread_context.hh
index eb12fee..7126a37 100644
--- a/src/arch/arm/fastmodel/CortexR52/thread_context.hh
+++ b/src/arch/arm/fastmodel/CortexR52/thread_context.hh
@@ -56,6 +56,7 @@
     bool translateAddress(Addr &paddr, Addr vaddr) override;

     void initFromIrisInstance(const ResourceMap &resources) override;
+    void sendFunctional(PacketPtr pkt) override;

// Since this CPU doesn't support aarch64, we override these two methods
     // and always assume we're 32 bit. More than likely we could be more

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icc824502faec5ac228003f0de7e9dbe26babe7ef
Gerrit-Change-Number: 52623
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang <yuhsi...@google.com>
Gerrit-Reviewer: Earl Ou <shunhsin...@google.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Yu-hsin Wang <yuhsi...@google.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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