Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52863 )
Change subject: tests: Replace master/slave terminology from tests scripts
......................................................................
tests: Replace master/slave terminology from tests scripts
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Change-Id: Id7aafc082c7e4cfc977e807141e63a3feb5a6348
---
M tests/gem5/memory/simple-run.py
M tests/gem5/configs/base_config.py
M tests/gem5/memory/memtest-run.py
M tests/gem5/cpu_tests/run.py
M tests/configs/memtest-filter.py
M tests/configs/memtest.py
6 files changed, 41 insertions(+), 31 deletions(-)
diff --git a/tests/configs/memtest-filter.py
b/tests/configs/memtest-filter.py
index cce7397..23b7550 100644
--- a/tests/configs/memtest-filter.py
+++ b/tests/configs/memtest-filter.py
@@ -50,7 +50,7 @@
system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain,
snoop_filter = SnoopFilter())
system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB',
assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.cpu_side = system.toL2Bus.mem_side_ports
# connect l2c to membus
system.l2c.mem_side = system.membus.slave
@@ -66,7 +66,7 @@
system.system_port = system.membus.slave
# connect memory to membus
-system.physmem.port = system.membus.master
+system.physmem.port = system.membus.mem_side_ports
# -----------------------
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index a957674..31ab14d 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -49,7 +49,7 @@
system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain)
system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB',
assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.cpu_side = system.toL2Bus.mem_side_ports
# connect l2c to membus
system.l2c.mem_side = system.membus.slave
@@ -65,7 +65,7 @@
system.system_port = system.membus.slave
# connect memory to membus
-system.physmem.port = system.membus.master
+system.physmem.port = system.membus.mem_side_ports
# -----------------------
diff --git a/tests/gem5/configs/base_config.py
b/tests/gem5/configs/base_config.py
index 9496f41..9867ede 100644
--- a/tests/gem5/configs/base_config.py
+++ b/tests/gem5/configs/base_config.py
@@ -108,8 +108,8 @@
system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain)
system.l2c = L2Cache(clk_domain=system.cpu_clk_domain,
size='4MB', assoc=8)
- system.l2c.cpu_side = system.toL2Bus.master
- system.l2c.mem_side = system.membus.slave
+ system.l2c.cpu_side = system.toL2Bus.mem_side_ports
+ system.l2c.mem_side = system.membus.cpu_side_ports
return system.toL2Bus
def init_cpu(self, system, cpu, sha_bus):
@@ -250,8 +250,8 @@
mem_mode = self.mem_mode,
multi_thread = (self.num_threads > 1))
if not self.use_ruby:
- system.system_port = system.membus.slave
- system.physmem.port = system.membus.master
+ system.system_port = system.membus.cpu_side_ports
+ system.physmem.port = system.membus.mem_side_ports
self.init_system(system)
return system
@@ -293,7 +293,7 @@
if self.use_ruby:
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
- system.iobus.master = system.ruby._io_port.slave
+ system.iobus.mem_side_ports = system.ruby._io_port.slave
else:
# create the memory controllers and connect them, stick with
# the physmem name to avoid bumping all the reference stats
@@ -308,12 +308,12 @@
system.physmem = [self.mem_class(range = r)
for r in system.mem_ranges]
for i in range(len(system.physmem)):
- system.physmem[i].port = system.membus.master
+ system.physmem[i].port = system.membus.mem_side_ports
# create the iocache, which by default runs at the system clock
system.iocache = IOCache(addr_ranges=system.mem_ranges)
- system.iocache.cpu_side = system.iobus.master
- system.iocache.mem_side = system.membus.slave
+ system.iocache.cpu_side = system.iobus.mem_side_ports
+ system.iocache.mem_side = system.membus.cpu_side_ports
def create_root(self):
system = self.create_system()
diff --git a/tests/gem5/cpu_tests/run.py b/tests/gem5/cpu_tests/run.py
index f6a1cf6..c17956e 100644
--- a/tests/gem5/cpu_tests/run.py
+++ b/tests/gem5/cpu_tests/run.py
@@ -43,7 +43,7 @@
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU-side port
@@ -83,10 +83,10 @@
tgts_per_mshr = 12
def connectCPUSideBus(self, bus):
- self.cpu_side = bus.master
+ self.cpu_side = bus.mem_side_ports
def connectMemSideBus(self, bus):
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
class MySimpleMemory(SimpleMemory):
@@ -134,8 +134,8 @@
if args.cpu == "AtomicSimpleCPU":
system.membus = SystemXBar()
- system.cpu.icache_port = system.membus.slave
- system.cpu.dcache_port = system.membus.slave
+ system.cpu.icache_port = system.membus.cpu_side_ports
+ system.cpu.dcache_port = system.membus.cpu_side_ports
else:
system.cpu.l1d = L1DCache()
system.cpu.l1i = L1ICache()
@@ -151,14 +151,14 @@
system.cpu.createInterruptController()
if m5.defines.buildEnv['TARGET_ISA'] == "x86":
- system.cpu.interrupts[0].pio = system.membus.master
- system.cpu.interrupts[0].int_master = system.membus.slave
- system.cpu.interrupts[0].int_slave = system.membus.master
+ system.cpu.interrupts[0].pio = system.membus.mem_side_ports
+ system.cpu.interrupts[0].int_master = system.membus.cpu_side_ports
+ system.cpu.interrupts[0].int_slave = system.membus.mem_side_ports
system.mem_ctrl = valid_mem[args.mem]()
system.mem_ctrl.range = system.mem_ranges[0]
-system.mem_ctrl.port = system.membus.master
-system.system_port = system.membus.slave
+system.mem_ctrl.port = system.membus.mem_side_ports
+system.system_port = system.membus.cpu_side_ports
process = Process()
process.cmd = [args.binary]
diff --git a/tests/gem5/memory/memtest-run.py
b/tests/gem5/memory/memtest-run.py
index 0cae42d..9b6625c 100644
--- a/tests/gem5/memory/memtest-run.py
+++ b/tests/gem5/memory/memtest-run.py
@@ -50,10 +50,10 @@
system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain)
system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB',
assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.cpu_side = system.toL2Bus.mem_side_ports
# connect l2c to membus
-system.l2c.mem_side = system.membus.slave
+system.l2c.mem_side = system.membus.cpu_side_ports
# add L1 caches
for cpu in cpus:
@@ -61,12 +61,12 @@
cpu.clk_domain = system.cpu_clk_domain
cpu.l1c = L1Cache(size = '32kB', assoc = 4)
cpu.l1c.cpu_side = cpu.port
- cpu.l1c.mem_side = system.toL2Bus.slave
+ cpu.l1c.mem_side = system.toL2Bus.cpu_side_ports
-system.system_port = system.membus.slave
+system.system_port = system.membus.cpu_side_ports
# connect memory to membus
-system.physmem.port = system.membus.master
+system.physmem.port = system.membus.mem_side_ports
# -----------------------
diff --git a/tests/gem5/memory/simple-run.py
b/tests/gem5/memory/simple-run.py
index 7cf9745..e2b8b0f 100644
--- a/tests/gem5/memory/simple-run.py
+++ b/tests/gem5/memory/simple-run.py
@@ -76,14 +76,14 @@
system.monitor.stackdist = StackDistProbe(verify = True)
# connect the traffic generator to the bus via a communication monitor
-system.cpu.port = system.monitor.slave
-system.monitor.master = system.membus.slave
+system.cpu.port = system.monitor.cpu_side_ports
+system.monitor.mem_side_ports = system.membus.cpu_side_ports
# connect the system port even if it is not used in this example
-system.system_port = system.membus.slave
+system.system_port = system.membus.cpu_side_ports
# connect memory to the membus
-system.physmem.port = system.membus.master
+system.physmem.port = system.membus.mem_side_ports
# -----------------------
# run simulation
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id7aafc082c7e4cfc977e807141e63a3feb5a6348
Gerrit-Change-Number: 52863
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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